HC805P18GRSSLASHD datasheet(45/111 Pages) NXP

45 / 111 page

GENERAL RELEASE SPECIFICATION

INPUT/OUTPUT PORTS

Rev. 1.0

SECTION 7

INPUT/OUTPUT PORTS

7.1 Introduction

In user mode, 20 bidirectional input/output (I/O) lines are arranged as two 8-bit I/O

ports (ports A and C), one 3-bit I/O port (port B), and one 1-bit I/O port (port D).

These ports are programmable as either inputs or outputs under software control

of the data direction registers (DDRs). An input-only pin is associated with port D.

7.2 Port A

Port A is an 8-bit bidirectional port which can share its pins with the IRQ interrupt

system as shown in Figure 7-1. Each port A pin is controlled by the corresponding

bits in a data direction register and a data register. The port A data register is

located at address $0000. The port A data direction register (DDRA) is located at

address $0004. Reset clears the DDRA, thereby initializing port A as an input port.

The port A data register is unaffected by reset.

Figure 7-1. Port A I/O Circuitry

READ $0000

WRITE $0000

READ $0004

DATA

TO IRQ INTERRUPT

SYSTEM

I/O

OUTPUT

INTERNAL HC05

DATA BUS

RESET

(RST)

WRITE $0004

DATA DIRECTION

MOR 2

100

µA

PULLUP

VDD

(PULLUP INHIBIT)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC805P18GRS/D Datasheet(PDF) 45 Page - NXP Semiconductors