HC805P18GRSSLASHD datasheet(52/111 Pages) NXP

52 / 111 page

GENERAL RELEASE SPECIFICATION

EEPROM

MC68HC805P18

8-2

In byte erase mode, only the selected byte is erased. In block mode, a 32-byte

block of EEPROM is erased. The EEPROM memory space is divided into four

32-byte blocks ($140–$15F, $160–$17F, $180–$19F, $1A0–$1BF), and doing

a block erase to any address within a block will erase the entire block. In bulk

erase mode, the entire 128-byte EEPROM section is erased.

LATCH — Latch Bit

When set, LATCH configures the EEPROM address and data bus for

programming. Writes to the EEPROM array cause the data bus and the address

bus to be latched. This bit is readable and writable, but reads from the array are

inhibited if the LATCH bit is set and a write to the EEPROM space has taken

place.

When clear, address and data buses are configured for normal operation. Reset

clears this bit.

EERC — EEPROM RC Oscillator Control

When this bit is set, the EEPROM section uses the internal RC oscillator instead

of the CPU clock. The RC oscillator is shared with the A/D converter, so this bit

should be set by the user when the internal bus frequency is below 1.5 MHz to

guarantee reliable operation of the EEPROM or A/D converter. After setting the

EERC bit, delay a time, tRCON, to allow the RC oscillator to stabilize. This bit is

readable and writable. The EERC bit is cleared by reset. The RC oscillator is

disabled while the MCU is in stop mode.

EEPGM — EEPROM Programming Power Enable

EEPGM must be written to enable (or disable) the EEPGM function. When set,

EEPGM turns on the charge pump and enables the programming (or erasing)

power to the EEPROM array. When clear, this power is switched off. This will

enable pulsing of the programming voltage to be controlled internally. This bit

can be read at any time, but can only be written to if LATCH = 1. If LATCH is not

set, then EEPGM cannot be set. LATCH and EEPGM cannot both be set with

one write if LATCH is cleared. EEPGM is cleared automatically when LATCH is

cleared. Reset clears this bit.

Table 8-1. Erase Mode Select

ER1

ER0

Mode

Program (no Erase)

Byte Erase

Block Erase

Bulk Erase

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC805P18GRS/D Datasheet(PDF) 52 Page - NXP Semiconductors

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