STM32U5A5QJ datasheet(328/382 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32U5Axxx

328/382

DS13543 Rev 1

5.3.35

OCTOSPI characteristics

Unless otherwise specified, the parameters given in Table 139 toTable 141 are derived from

tests performed under the ambient temperature, fAHB frequency and VDD supply voltage

conditions summarized in Table 33, with the following configuration:

•

Output speed set to OSPEEDRy[1:0] = 10

•

Delay block enabled for DTR (with DQS)/HyperBus

•

Measurement points done at 0.5 × VDD level

•

I/O compensation cell activated

•

HSLV activated when VDD ≤ 2.7 V

•

Voltage scaling range 1 unless otherwise specified

Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate

function characteristics.

Table 137. Switching characteristics for NAND Flash read cycles(1)

Symbol

Parameter

Min

Max

Unit

tw(N0E)

FMC_NOE low width

4 × tHCLK - 0.5 4 × tHCLK + 0.5

tsu(D-NOE)

FMC_D[15-0] valid data before FMC_NOE high

th(NOE-D)

FMC_D[15-0] valid data after FMC_NOE high

td(ALE-NOE)

FMC_ALE valid before FMC_NOE low

3 × tHCLK + 0.5

th(NOE-ALE)

FMC_NWE high to FMC_ALE invalid

4 × tHCLK - 1

1. Evaluated by characterization. Not tested in production.

Table 138. Switching characteristics for NAND Flash write cycles(1)

Symbol

Parameter

Min

Max

Unit

tw(NWE)

FMC_NWE low width

4 × tHCLK - 0.5

4 × tHCLK + 0.5

tv(NWE-D)

FMC_NWE low to FMC_D[15-0] valid

th(NWE-D)

FMC_NWE high to FMC_D[15-0] invalid

2 × tHCLK + 1

td(D-NWE)

FMC_D[15-0] valid before FMC_NWE high

5 × tHCLK - 5

td(ALE_NWE)

FMC_ALE valid before FMC_NWE low

3 × tHCLK + 0.5

th(NWE-ALE)

FMC_NWE high to FMC_ALE invalid

2 × tHCLK - 0.5

1. Evaluated by characterization. Not tested in production.

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