ST25R3920B datasheet(28/158 Pages) STMICROELECTRONICS

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Application information

ST25R3920B

28/158

DS13890 Rev 4

Correlator

The correlators correlate the incoming filtered subcarrier with 848 kHz. The aim of the

correlation is to maximize the system sensitivity at 848 kHz, while rejecting other

frequencies. There are two correlators in the system for AM (or I) channel and PM (or Q)

channel.

Correlator settings are defined in Correlator configuration register 1 and Correlator

configuration register 2.

RSSI

The receiver also performs the RSSI (received signal strength indicator) measurement for

both channels. The RSSI measurement is started after the rising edge of rx_on. It stays

active while the signal rx_on is high and frozen while rx_on is low. It is a peak hold system

where the value can only increase from initial 0 value. Every time the AGC reduces the gain

the RSSI measurement is reset and starts from 0. The result of RSSI measurements is a

4-bit value that can be observed by reading the RSSI display register. The LSB step is

2.8 dB, the maximum value is Dh (13d).

Since the RSSI measurement is of peak hold type, the result does not follow any variations

in the signal strength (the highest value will be kept). To follow RSSI variation it is possible

to reset RSSI bits and restart the measurement by sending direct command Clear RSSI.

Clock extractor

The clock extractor observes the RFI1 and RFI2 differential signal and provides a clock

signal synchronous with the incoming RF field. The extracted clock is used for synchronous

demodulation, for correct frame delay time and for correct data timing during passive

transmission. The clock extractor is active down to 60 mVPP input signal.

4.2.3

Antenna tuning

The ST25R3920B supports antenna tuning through external variable capacitors. The

variable capacitor is connected on its position in the matching network, and the tuning

control voltage is connected to one of the control output pins (AAT_A, AAT_B).

The variable capacitors can be connected in series and parallel configurations in the

matching network. Further information on the various configuration options can be found in

the application note AN5322, available on www.st.com.

The phase and amplitude detector block is used for resonance frequency checking. The

algorithm in the MCU evaluates the result and adjusts the tuning voltages at AAT_A and

AAT_B output pins via the Antenna tuning control register 1 and Antenna tuning control

The AAT_A/B pin voltages are actively set according to Antenna tuning control register 1

and Antenna tuning control register 2 when en and aat_en option bits are both set.

If aat_en=1 and en=0, the AAT_A/B voltages are set to a fixed value between 1.5 and 2.2 V

(typically 1.9 V).

ST25R3920B Datasheet(PDF) 28 Page - STMicroelectronics

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