ISL8200AMMREP datasheet(14/24 Pages) RENESAS

14 / 24 page

ISL8200AMM

FN8287 Rev 2.00

Page 14 of 24

June 3, 2015

Output Capacitors

The ISL8200AMMREP is designed for low output voltage ripple.

The output voltage ripple and transient requirements can be met

with bulk output capacitors (COUT) with low enough Equivalent

Series Resistance (ESR); the recommended ESR is <10mΩ.

When the total ESR is below 4mΩ, a capacitor (CFF) between

2.2nF-10nF is recommended; CFF is placed in parallel with RSET,

in between the VOUT and VOUT_SET pin. COUT can be a low ESR

tantalum capacitor, a low ESR polymer capacitor or a ceramic

capacitor. Typical output capacitance is 300µF. More decoupling

capacitors may be required to reduce noise, reduce output ripple,

and improve transient performance. The internally optimized

loop compensation provides sufficient stability margins for all

ceramic capacitor applications with a recommended total value

of 300µF per phase. Additional output filtering may be needed if

further reduction of output ripple or dynamic transient spike is

required.

Using Multiple Phases

The ISL8200AMMREP can be easily connected in parallel with

other ISL8200AMMREP modules and current share providing an

additional 10A per phase. For 2 phases, simply follow the

schematic shown in Figure 4. A rough summary shows that the

modules share VIN, VOUT, GND and have their ISHARE pins tied

together with a 10kΩ resistor to ground (per phase). When using

3 phases or more, it is recommended that you add the following

circuitry (see Figure 23) to ensure proper startup. The circuit

shown in Figure 23 ensures proper startup by injecting current

into the ISHARE line until all phases are ready to start regulating.

For additional phases, the RC time constant, using RINC and CG,

might have to be adjusted to increase the turn on time of the

PFET (QSHR). For 3-4 phases, these are the values, RINC = 243k,

RPH1 = 15k, QSHR = Small Signal PFET, CG = 22nF).

Functional Description

Initialization

The ISL8200AMMREP requires VCC and PVCC to be biased by a

single supply. Power-On Reset (POR) circuits continually monitor

the bias voltages (PVCC and VCC) and the voltage at the EN pin.

The POR function initiates soft-start operation 384 clock cycles

after the EN pin voltage is pulled to be above 0.8V, all input

supplies exceed their POR thresholds and the PLL locking time

expires. The enable pin can be used as a voltage monitor and to

set desired hysteresis with an internal 30µA sinking current

going through an external resistor divider. The sinking current is

disengaged after the system is enabled. This feature is especially

designed for applications that require higher input rail POR for

better undervoltage protection. For example, in 12V applications,

RUP = 53.6k and RDOWN = 5.23k will set the turn-on threshold

(VEN_RTH) to 10.6V and turn-off threshold (VEN_FTH) to 9V, with

1.6V hysteresis (VEN_HYS). These numbers are explained in

Figure 28 on page 15.

During shutdown or fault conditions, the soft-start is quickly reset

while UGATE and LGATE immediately change state (<100ns)

upon the input dropping below the POR threshold.

Soft-Start

The ISL8200AMMREP has an internal digital pre-charged

soft-start circuitry, which has a rise time inversely proportional to

the switching frequency and is determined by a digital counter

that increments with every pulse of the phase clock. The full

soft-start time from 0V to 0.6V can be estimated by Equation 5.

The ISL8200AMMREP has the ability to work under a pre-charged

output. The PWM outputs will not be fed to the drivers until the first

PWM pulse is seen. The low side MOSFET is held low for the first

clock cycle to provide charge for the bootstrap capacitor. If the

pre-charged output voltage is greater than the final target level but

less than the 113% setpoint, switching will not start until the output

voltage is reduced to the target voltage and the first PWM pulse is

generated. The maximum allowable pre-charged level is 113%. If

the pre-charged level is above 113% but below 120%, the output

will hiccup between 113% (LGATE turns on) and 87% (LGATE turns

off) while EN is pulled low. If the pre-charged load voltage is above

120% of the targeted output voltage, then the controller will be

latched off and not be able to power-up.

ISFETDRV (PHASE 2)

ISFETDRV (PHASE 3)

ISFETDRV (PHASE 1)

ADD ADDITIONAL

DIODES PER PHASE

VCC (PHASE 1)

ISHARE

QSHR

RINC

RPH1

DPH2

FIGURE 23. STARTUP CIRCUITRY

FIGURE 24. SOFT-START INITIALIZATION LOGIC

VCC POR

PVCC POR

EN POR

SOFT-START

HIGH = ABOVE POR; LOW = BELOW POR

OF MODULE

AND

384

PLL LOCKING

CYCLES

tSS

2560

fSW

--------------

(EQ. 5)

VOUT TARGET VOLTAGE

0.0V

tss

2560

fSW

--------------



FIRST PWM PULSE

-100mV

FIGURE 25. SOFT-START WITH VOUT = 0V

SS SETTLING AT VREF + 100mV

tss_DLY

384

fSW

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

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