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ADMFM2000ABVZ Datasheet(PDF) 8 Page - Analog Devices |
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ADMFM2000ABVZ Datasheet(HTML) 8 Page - Analog Devices |
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8 / 28 page  Data Sheet ADMFM2000 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS analog.com Rev. 0 | 8 of 28 Table 5. Pin Function Descriptions (Continued) Pin No. Mnemonic Type Description Power Supplies B2 VGG_RFAMP_1 Input Optional Gain Control Voltage for Channel 1 LNA. This pin is internally self-biased and must normally be left open. B4 VDD_LNA_1 Input Analog 5.0 V Input for the Channel 1 LNA. B18 VSS_DSAS Input Analog −5.0 V for DSAs. D18 VDD_IF_1 Input Analog 5.0 V Input for the Channel 1 IF Amplifier and Channel 1 DSA. E4 VDD_LO_DRIVER_1 Input Analog 5.0 V Input for the Channel 1 LO Driver. F4 VGG_LOAMP_1 Input Optional Gain Control Voltage for Channel 1 LO amplifier. This pin is internally self-biased and must normally be left open. G4 VGG_LOAMP_2 Input Optional Gain Control Voltage for Channel 2 LO Amplifier. This pin is internally self-biased and must normally be left open. J18 VDD_IF_2 Input Analog 5.0 V Input for the Channel 2 IF amplifier and Channel 2 DSA. K4 VGG_RFAMP_2 Input Optional Gain Control Voltage for the Channel 2 LNA. This pin is internally self-biased and must normally be left open. K7 VDD_LO_DRIVER_2 Input Analog 5.0 V Input for the Channel 2 LO Driver. M4 VDD_LNA_2 Input Analog 5.0 V Input for the Channel 2 LNA. A5, A7, A9, A11, A13, B3, B5, B7 to B9, B11, B13, B14, B17, C1 to C13, C17, C18, D3 to D13, D16, D17, E1 to E3, E16 to E19, F2, F3, F6 to F14, F16, F17, G1 to G3, G6 to G14, G16 to G19, H3, H4, H6 to H14, H16 to H18, J1 to J4, J16, J17, K1 to K3, K5, K6, K8 to K13, K15 to K19, L3 to L13, L17, M1 to M3, M5, M7 to M9, M11, M13, M17 to M19, N5, N7, N9, N11, N13 GND Input/Output Ground. Control Signals B15 SW1_CTRL_A Input Channel 1 Switch Control Input A. The SW1_CTRL_A pin must always be kept at a valid logic level (refer to Table 1). B16 SW1_CTRL_B Input Channel 1 Switch Control Input B. The SW1_CTRL_B pin must always be kept at a valid logic level (refer to Table 1). K14 SW2_CTRL_B Input Channel 2 Switch Control Input B. The SW2_CTRL_A pin must always be kept at a valid logic level (refer to Table 1). L14 SW2_CTRL_A Input Channel 2 Switch Control Input A. The SW2_CTRL_B pin must always be kept at a valid logic level (refer to Table 1). Channel 1 DSA Control Inputs D15 DSA1_V0 Input Channel 1 DSA Parallel Control Voltage Inputs for the Required Attenuation. There is no internal pull-up or pull-down resistor on these pins. Therefore, the DSA1_Vx pins must always be kept at a valid logic level (5 V VINH or 0 V VINL) and not be left floating. D14 DSA1_V1 Input C14 DSA1_V2 Input C15 DSA1_V3 Input C16 DSA1_V4 Input Channel 2 DSA Control Inputs M14 DSA2_V0 Input Channel 2 DSA Parallel Control Voltage Inputs for the Required Attenuation. There is no internal pull-up or pull-down resistor on these pins. Therefore, the DSA2_Vx pins must always be kept at a valid logic level (refer to Table 1) and not be left floating. M15 DSA2_V1 Input M16 DSA2_V2 Input L15 DSA2_V3 Input L16 DSA2_V4 Input |
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