FIDO5210BBCZ-R7 datasheet(19/21 Pages) AD

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Data Sheet

fido5100/fido5200

APPLICATIONS INFORMATION

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Rev. G | 19 of 21

requirement for EtherCAT designs (and recommended for other

designs) to use the CLKOUT signal from the REM switch as the

clock source for the PHYs. This approach minimizes jitter as much

as possible.

CLKOUT from the REM switch is a 25 MHz clock signal generated

from the 25 MHz input clock to the REM switch using the internal

PLL of the REM switch. The PHY uses the 25 MHz CLKOUT signal

to generate the MII receive (Rx) and transmit (Tx) clock inputs

(P1_RXCLK, P1_TXCLK, P2_RXCLK, and P2_TXCLK pins) to the

REM switch.

For RMII, the REM switch generates the required 50 MHz clock for

the RMII interface. The clock is generated from the 25 MHz input

clock to the REM switch using the internal PLL of the REM switch.

As with all clock signals, take care when routing these signals to

minimize noise and loading effects.

Management Data Input/Output (MDIO)

All PHYs require configuration and can provide some type of status

information in return. Each PHY is different, but most PHYs use

a management data input/output (MDIO) interface to communicate

this configuration and status. The REM switch does not provide

separate communication to the PHYs. The host processor paired

with the REM switch is required to provide this PHY communica-

tion.

Contact Analog Devices, Inc., technical support regarding questions

about PHY settings or the MDIO interface.

RAPID PLATFORM GENERATION 2 (RPG2)

SOLUTION

When using the RapID Platform Generation 2 (RPG2) solu-

tion with the embedded reference design, the fido5110BBCZ,

fido5110CBCZ, fido5210BBCZ, and fido5210CBCZ are the only

versions of the real-time Ethernet multiprotocol switch that work

with the industrial Ethernet protocols related to this solution. See

the Ordering Guide section.

FIDO5210BBCZ-R7 Datasheet(PDF) 19 Page - Analog Devices