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PIC18F6X2X Datasheet(PDF) 162 Page - Microchip Technology |
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PIC18F6X2X Datasheet(HTML) 162 Page - Microchip Technology |
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162 / 386 page  PIC18F6X2X/8X2X DS39612A-page 160 Advance Information 2003 Microchip Technology Inc. 17.1 ECCP Outputs and Configuration Each of the enhanced CCP modules may have up to four PWM outputs, depending on the selected operating mode. These outputs, designated PxA through PxD, are multiplexed with various I/O pins. Some ECCP pin assignments are constant, while others change based on device configuration. For those pins that do change, the controlling bits are: • CCP2MX configuration bit (CONFIG3H<0>) • ECCPMX configuration bit (CONFIG3H<1>) • Program Memory mode (set by configuration bits CONFIG3L<1:0>) The pin assignments for the enhanced CCP modules are summarized in Table 17-1, Table 17-2 and Table 17-3. To configure the I/O pins as PWM outputs, the proper PWM mode must be selected by setting the PxMx and CCPxMx bits (CCPxCON<7:6> and <3:0>, respectively). The appropriate TRIS direction bits for the corresponding port pins must also be set as outputs. 17.1.1 USE OF CCP4 AND CCP5 WITH ECCP1 AND ECCP3 Only ECCP2 module has four dedicated output pins available for use. Assuming that the I/O ports or other multiplexed functions on those pins are not needed, they may be used whenever needed without interfering with any other CCP module. ECCP1 and ECCP3, on the other hand, only have three dedicated output pins: CCPx/P3A, PxB, and PxC. Whenever these modules are configured for Quad PWM mode, the pin normally used for CCP4 or CCP5 becomes the D output pins for ECCP3 and ECCP1, respectively. The CCP4 and CCP5 modules remain functional but their outputs are overridden. 17.1.2 ECCP MODULE OUTPUTS AND PROGRAM MEMORY MODES For PIC18F8X2X devices, the Program Memory mode of the device (Section 4.1.1) impacts both pin multiplexing and the operation of the module. The ECCP2 input/output (CCP2/P2A) can be multi- plexed to one of three pins. By default, this is RC1 for all devices; in this case, the default is when CCP2MX is set and the device is operating in Microcontroller mode. With PIC18F8X2X devices, three other options exist. When CCP2MX is not set (= 0) and the device is in Microcontroller mode, CCP2/P2A is multiplexed to RE7; in all other Program Memory modes, it is multiplexed to RB3. The final option is for CCP2MX to be set while the device is operating in one of the three other Program Memory modes. In this case, ECCP1 and ECCP3 oper- ate as compatible (i.e., single output) CCP modules. The pins used by their other outputs (PxB through PxD) are available for other multiplexed functions. ECCP2 continues to operate as an enhanced CCP module regardless of the Program Memory mode. TABLE 17-1: PIN CONFIGURATIONS FOR ECCP1 ECCP Mode CCP1CON Configuration RC2 RE6 RE5 RG4 RH7 RH6 All PIC18F6X2X devices: Compatible CCP 00xx11xx CCP1 RE6 RE5 RG4/CCP5 n/a n/a Dual PWM 10xx11xx P1A P1B RE5 RG4/CCP5 n/a n/a Quad PWM x1xx11xx P1A P1B P1C P1D n/a n/a PIC18F8X2X devices, ECCPMX = 1, Microcontroller mode: Compatible CCP 00xx11xx CCP1 RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14 Dual PWM 10xx11xx P1A P1B RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14 Quad PWM x1xx11xx P1A P1B P1C P1D RH7/AN15 RH6/AN14 PIC18F8X2X devices, ECCPMX = 0, Microcontroller mode: Compatible CCP 00xx11xx CCP1 RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14 Dual PWM 10xx11xx P1A RE6/AD14 RE5/AD13 RG4/CCP5 P1B RH6/AN14 Quad PWM x1xx11xx P1A RE6/AD14 RE5/AD13 P1D P1B P1C PIC18F8X2X devices, ECCPMX = 1, all other Program Memory modes: Compatible CCP 00xx11xx CCP1 RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14 Legend: x = Don’t care, n/a = Not available. Shaded cells indicate pin assignments not used by ECCP1 in a given mode. Note 1: With ECCP1 in Quad PWM mode, CCP5’s output is overridden by P1D; otherwise CCP5 is fully operational. |
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