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PIC18F6X2X Datasheet(PDF) 165 Page - Microchip Technology

Part # PIC18F6X2X
Description  64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D
PDF  386 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F6X2X Datasheet(HTML) 165 Page - Microchip Technology

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 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 163
PIC18F6X2X/8X2X
FIGURE 17-1:
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
17.4.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPRxL:CCPxCON<5:4>. The PWM duty cycle is
calculated by the equation:
CCPR1L and CCP1CON<5:4> can be written to at any
time but the duty cycle value is not copied into
CCPR1H until a match between PR2 and TMR2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read only register.
The CCPRxH register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM opera-
tion. When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bits
of the TMR2 prescaler, the CCP1 pin is cleared. The
maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
TABLE 17-4:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
RQ
S
Duty Cycle Registers
CCP1CON<5:4>
Clear Timer,
set CCP1 pin and
latch D.C.
Note: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit
time base.
TRISx<x>
CCP1/P1A
TRISx<x>
P1B
TRISx<x>
TRISx<x>
P1D
Output
Controller
P1M1<1:0>
2
CCP1M<3:0>
4
ECCP1DEL
CCP1/P1A
P1B
P1C
P1D
P1C
PWM Duty Cycle =
(CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
(
)
PWM Resolution (max) =
FOSC
FPWM
log
log(2)
bits
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz
156.25 kHz
312.50 kHz
416.67 kHz
Timer Prescaler (1, 4, 16)
16
41111
PR2 Value
FFh
FFh
FFh
3Fh
1Fh
17h
Maximum Resolution (bits)
10
10
10
8
7
6.58



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