TMP88CS38BFG datasheet(94/218 Pages) TOSHIBA

94 / 218 page

TMP88CS38B/CM38B/CP38B

2007-09-12

88CS38B-94

(7) Start/stop condition generation

When the BB (Bit5 in SBICRB) is “0”, a slave address and a direction bit which are

set to the SBIDBR are output on a bus after generating a start condition by writing “1”

to the MST, TRX, BB and PIN. It is necessary to set transmitted data to the SBIDBR

and set “1” to ACK beforehand.

Figure 2.9.9 Start Condition Generation and Slave Address Generation

When the BB is “1”, sequence of generating a stop condition is started by writeng “1”

to the MST, TRX and PIN, and “0” to the BB. Do not modify the contents of MST, TRX,

BB and PIN until a stop condition is generated on a bus.

Figure 2.9.10 Stop Condition Generation

When a stop condition is generated and the SCL line on a bus is pulled down to low

level by another device, a stop condition is generated after releasing the SCL line.

The bus condition can be indicated by reading the contents of the BB (Bit5 in

SBISRB). The BB is set to “1” when a start condition on a bus is detected and is cleared

to “0” when a stop condition is detected.

(8) Interrupt service request and cancel

When a serial bus interface circuit is in the master mode and transferring a number

of clocks set by the BC and the ACK is complete, a serial bus interface interrupt

request (INTSBI) is generated.

In the slave mode, the conditions of generating INTSBI are follows:

•

At the end of acknowledge signal when the received slave address matches to the

value set by the I2CAR

•

At the end of acknowledge signal when a “GENERAL CALL” is received

•

At the end of transferring or receiving after matching of slave address or receiving

of “GENRAL CALL”

When a serial bus interface interrupt request occurs, the PIN (Bit4 in SBISR) is

cleared to “0”. During the time that the PIN is “0”, the SCL pin is pulled down to low

level.

Either writing data to SBIDBR or reading data from the SBIDBR sets the PIN to “1”.

The time from the PIN being set to “1” until the SCL pin is released takes tLOW.

Although the PIN (Bit4 in SBICRB) can be set to “1” by the program, the PIN can not

be cleared to “0” by the program.

Note:

If the arbitration lost occurs, when the slave address does not match, the PIN is not

cleared to “0” even thought INTSBI is generated.

SCL pin

SDA pin

Start

condition

slave address and the direction bit

Acknowledge

signal

345678

R/ W

SDA pin

SCL pin

Stop condition

TMP88CS38BFG Datasheet(PDF) 94 Page - Toshiba Semiconductor

TMP88CS38BFG Datasheet(HTML) 94 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL