S29GL01GS10DFIV13 datasheet(34/108 Pages) CYPRESS

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Document Number: 001-98285 Rev. *R

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S29GL01GS/S29GL512S

S29GL256S/S29GL128S

5.5

Status Monitoring

There are three methods for monitoring EA status. Previous generations of the S29GL flash family used the methods called Data

Polling and Ready/Busy# (RY/BY#) Signal. These methods are still supported by the S29GL-S family. One additional method is

reading the Status Register.

5.5.1

Status Register

The status of program and erase operations is provided by a single 16-bit status register. The status is receiver by writing the Status

captured (by the rising edge of WE#) into the register and the ASO is entered. The contents of the status register is aliased (overlaid)

on the full memory address space. Any valid read (CE# and OE# low) access while in the Status Register ASO will exit the ASO

(with the rising edge of CE# or OE# for tCEPH/tOEPH time) and return to the address space map in use when the Status Register

Read command was issued.

The status register contains bits related to the results - success or failure - of the most recently completed Embedded Algorithms

(EA):



Erase Status (bit 5),



Program Status (bit 4),



Write Buffer Abort (bit 3),



Sector Locked Status (bit 1),



RFU (bit 0).

and, bits related to the current state of any in process EA:



Device Busy (bit 7),



Erase Suspended (bit 6),



Program Suspended (bit 2),

The current state bits indicate whether an EA is in process, suspended, or completed.

The upper 8 bits (bits 15:8) are reserved. These have undefined High or Low value that can change from one status read to another.

These bits should be treated as don't care and ignored by any software reading status.

The Soft Reset Command will clear to 0 bits [5, 4, 1, 0] of the status register if Status Register bit 3 =0. It will not affect the current

state bits. The Clear Status Register Command will clear to 0 the results related bits of the status register but will not affect the

current state bits.

Notes:

1. Bits 15 thru 8, and 0 are reserved for future use and may display as 0 or 1. These bits should be ignored (masked) when checking status.

2. Bit 7 is 1 when there is no Embedded Algorithm in progress in the device.

3. Bits 6 thru 1 are valid only if Bit 7 is 1.

4. All bits are put in their reset status by cold reset or warm reset.

Table 5.2 Status Register

Bit #

15:8

543210

Bit

Description

Reserved

Device

Ready Bit

Erase

Suspend

Status Bit

Erase Status

Bit

Program

Status Bit

Write Buffer

Abort Status

Bit

Program

Suspend

Status Bit

Sector Lock

Status Bit

Reserved

Bit Name

DRB

ESSB

ESB

PSB

WBASB

PSSB

SLSB

Reset Status

000000

Busy Status

Invalid

Ready

Status

0 = No Erase

Suspension

1 = Erase in

Suspension

0 = Erase

successful

1 = Erase

fail

0 = Program

successful

1 = Program

fail

0 = Program

not aborted

1 = Program

aborted

during Write

to Buffer

command

0 = No

Program in

suspension

1 = Program

suspension

0 = Sector

not locked

during

operation

1 = Sector

locked error

S29GL01GS10DFIV13 Datasheet(PDF) 34 Page - Cypress Semiconductor

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