S29GL01GS10DFIV13 datasheet(67/108 Pages) CYPRESS

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Document Number: 001-98285 Rev. *R

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S29GL01GS/S29GL512S

S29GL256S/S29GL128S

9.3

Power Conservation Modes

9.3.1

Interface Standby

Standby is the default, low power, state for the interface while the device is not selected by the host for data transfer (CE# = High).

All inputs are ignored in this state and all outputs except RY/BY# are high impedance. RY/BY# is a direct output of the EAC, not

controlled by the Host Interface.

9.3.2

Automatic Sleep

The automatic sleep mode reduces device interface energy consumption to the sleep level (ICC6) following the completion of a

random read access time. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. While in

sleep mode, output data is latched and always available to the system. Output of the data depends on the level of the OE# signal

but, the automatic sleep mode current is independent of the OE# signal level. Standard address access timings (tACC or tPACC)

provide new data when addresses are changed. ICC6 in DC Characteristics on page 72 represents the automatic sleep mode current

specification.

Automatic sleep helps reduce current consumption especially when the host system clock is slowed for power reduction. During

slow system clock periods, read and write cycles may extend many times their length versus when the system is operating at high

speed. Even though CE# may be Low throughout these extended data transfer cycles, the memory device host interface will go to

the Automatic Sleep current at tACC + 30 ns. The device will remain at the Automatic Sleep current for tASSB. Then the device will

transition to the standby current level. This keeps the memory at the Automatic Sleep or standby power level for most of the long

duration data transfer cycles, rather than consuming full read power all the time that the memory device is selected by the host

system.

However, the EAC operates independent of the automatic sleep mode of the host interface and will continue to draw current during

an active Embedded Algorithm. Only when both the host interface and EAC are in their standby states is the standby level current

achieved.

9.4

Read

9.4.1

Read With Output Disable

When the CE# signal is asserted Low, the host system memory controller begins a read or write data transfer. Often there is a period

at the beginning of a data transfer when CE# is Low, Address is valid, OE# is High, and WE# is High. During this state a read access

is assumed and the Random Read process is started while the data outputs remain at high impedance. If the OE# signal goes Low,

the interface transitions to the Random Read state, with data outputs actively driven. If the WE# signal is asserted Low, the interface

transitions to the Write state. Note, OE# and WE# should never be Low at the same time to ensure no data bus contention between

the host system and memory.

9.4.2

Random (Asynchronous) Read

When the host system interface selects the memory device by driving CE# Low, the device interface leaves the Standby state. If

WE# is High when CE# goes Low, a random read access is started. The data output depends on the address map mode and the

address provided at the time the read access is started.

The data appears on DQ15-DQ0 when CE# is Low, OE# is Low, WE# remains High, address remains stable, and the asynchronous

access times are satisfied. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip

enable access time (tCE) is the delay from stable CE# to valid data at the outputs. In order for the read data to be driven on to the

data outputs the OE# signal must be Low at least the output enable time (tOE) before valid data is available.

At the completion of the random access time from CE# active (tCE), address stable (tACC), or OE# active (tOE), whichever occurs

latest, the data outputs will provide valid read data from the currently active address map mode. If CE# remains Low and any of the

AMAX to A4 address signals change to a new value, a new random read access begins. If CE# remains Low and OE# goes High the

interface transitions to the Read with Output Disable state. If CE# remains Low, OE# goes High, and WE# goes Low, the interface

transitions to the Write state. If CE# returns High, the interface goes to the Standby state. Back to Back accesses, in which CE#

remains Low between accesses, requires an address change to initiate the second access. See Asynchronous Read Operations

on page 78.

S29GL01GS10DFIV13 Datasheet(PDF) 67 Page - Cypress Semiconductor

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