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S29GL01GS10DFIV13 Datasheet(PDF) 88 Page - Cypress Semiconductor |
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S29GL01GS10DFIV13 Datasheet(HTML) 88 Page - Cypress Semiconductor |
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88 / 108 page  Document Number: 001-98285 Rev. *R Page 88 of 108 S29GL01GS/S29GL512S S29GL256S/S29GL128S Figure 11.18 Toggle Bit Timing Diagram (During Embedded Algorithms) Note: 1. DQ6 will toggle at any read address while the device is busy. DQ2 will toggle if the address is within the actively erasing sector. Figure 11.19 DQ2 vs. DQ6 Relationship Diagram Note: 1. The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the erase-suspended sector. 11.4.3 Alternate CE# Controlled Write Operations Table 11.10 Alternate CE# Controlled Write Operations Parameter Description VIO = 2.7 V to VCC VIO = 1.65 V to VCC Unit JEDEC Std tAVAV tWC Write Cycle Time (Note 1) Min 60 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# Low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 45 ns tAHT Address Hold Time From CE# or OE# High during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 30 ns tWHDX tDH Data Hold Time Min 0 ns tCEPH CE# High during toggle bit polling Min 20 ns t0EPH OE# High during toggle bit polling Min 20 ns OE# CE# WE# Addresses tOEH tDH tAHT tASO tOEPH tOE Valid Data (first read) (second read) (stops toggling) tCEPH tAHT tAS DQ2 and DQ6 Valid Data Valid Status Valid Status Valid Status RY/BY# Enter Erase Erase Erase Enter Erase Suspend Program Erase Suspend Read Erase Suspend Read Erase WE# DQ6 DQ2 Erase Complete Erase Suspend Suspend Program Resume Embedded Erasing |
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