STM32G030F6 datasheet(60/94 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32G030x6/x8

60/94

DS12991 Rev 1

5.3.14

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 48 are derived from tests

performed under the conditions summarized in Table 21: General operating conditions. All

I/Os are designed as CMOS- and TTL-compliant.

Table 48. I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL(1)

I/O input low level

voltage

All

VDD(min) < VDDIO1 < 3.6 V

0.3 x VDDIO1

(2)

0.39 x VDDIO1

- 0.06 (3)

VIH(1)

I/O input high level

voltage

All

VDD(min) < VDDIO1 < 3.6 V

0.7 x VDDIO1(

0.49 x VDDIO1

+ 0.26(3)

Vhys(3) I/O input hysteresis

FT_xx,

NRST

VDD(min) < VDDIO1 < 3.6 V

200

Ilkg

Input leakage

current(3)

All

except

FT_e

0 < VIN ≤ VDDIO1

±70

VDDIO1 ≤ VIN ≤ VDDIO1+1 V

600(4)

VDDIO1 +1 V < VIN ≤

5.5 V(3)

150(4)

FT_e

(5)

0 < VIN < VDDIO1

µA

RPU

Weak pull-up

equivalent resistor

(6)

VIN = VSS

kΩ

RPD

Weak pull-down

equivalent resistor(6)

VIN = VDDIO1

kΩ

CIO

I/O pin capacitance

1. Refer to Figure 16: I/O input characteristics.

2. Tested in production.

3. Guaranteed by design.

4. This value represents the pad leakage of the I/O itself. The total product pad leakage is provided by this formula:

ITotal_Ileak_max = 10 µA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).

5. FT_e with diode enabled. Input leakage current of FT_e I/Os with the diode disabled is the same as standard I/Os.

6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

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