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STM32G030F6 Datasheet(PDF) 69 Page - STMicroelectronics |
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STM32G030F6 Datasheet(HTML) 69 Page - STMicroelectronics |
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69 / 94 page ![]() DS12991 Rev 1 69/94 STM32G030x6/x8 Electrical characteristics 80 8 bits 1.5 43 82 3.5 100 1500 7.5 214 3900 12.5 357 6800 19.5 557 12000 39.5 1129 27000 79.5 2271 50000 160.5 4586 50000 6 bits 1.5 43 390 3.5 100 2200 7.5 214 5600 12.5 357 10000 19.5 557 15000 39.5 1129 33000 79.5 2271 50000 160.5 4586 50000 1. Guaranteed by design. 2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and disabled when VDDA ≥ 2.4 V. Table 56. ADC accuracy(1)(2)(3) Symbol Parameter Conditions(4) Min Typ Max Unit ET Total unadjusted error VDDA=VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range -3 6.5 LSB EO Offset error VDDA=VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range -1.5 4.5 LSB EG Gain error VDDA=VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range -3 5 LSB ED Differential linearity error VDDA=VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range -1.2 1.5 LSB EL Integral linearity error VDDA=VREF+ < 3.6 V; fADC = 35 MHz; fs ≤ 2.5 MSps; TA = entire range -2.5 3 LSB Table 55. Maximum ADC RAIN . (continued) Resolution Sampling cycle at 35 MHz Sampling time at 35 MHz [ns] Max. RAIN(1)(2) (Ω) |
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