L99LDLH32 datasheet(114/142 Pages) STMICROELECTRONICS

114 / 142 page

FTP and RAM memory mapping

L99LDLH32

114/142

DS12879 Rev 6

7.2.7

Device FTP Configuration - Row_12

Figure 86. Device FTP Configuration - Row_12

Address 0xCh

Access

R/W

Data Byte 15

Data Byte 0

bit

127

bit

126

bit

125

bit

124

bit

123

bit

122

bit

121

bit

120

..........................................

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Reserved

PWM_DUTY_ALL

Table 69. Row_12

Bit

Name

Default

Description

127-120

Reserved

119-117

DITHERING

See Table 39

116-112

CAN SAMPLING POINT

See Table 70

111-104

Reserved

103-96

PG_TH_VPRE_REG

Power Good Threshold for VPRE_REG adjustable

in 157 mV steps (as in the RAM, see Table 37)

95-93

Reserved

SYNC_I/O_M/S

Commander/Responder SYNC_I/O:

Synchronization of PWM

frequency and phase between Commander and

Responder Devices

1: Responder Mode selected. SYNC_I/O is input.

Clock

frequency and phase signal on the SYNC_I/O line

is used

to synchronize own clock

0 (default): Commander Mode selected. SYNC_I/O

is output.

Device Clock frequency with scaler and phase

signal is

transfered to the SYNC_I/O line

91-90

POR_DELAY

Power on Reset Delay Time t_POR_DELAY; delay

time before activating outputs

in Fail Safe / Stand alone mode after POR

00: 0 ms

01: 25 ms

10: 50 ms

11: 100 ms

Reserved

STH_DET_EN

Short circuit detection for channels mapped to

VPRE_REG

0: short circuit detection disabled

1: short circuit detection enabled

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