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STM32WB09XE Datasheet(PDF) 14 Page - STMicroelectronics

Part # STM32WB09XE
Description  Ultra-low power wireless 32-bit MCU Arm®-based Cortex®-M0 with Bluetooth® LE and 2.4 GHz radio solution
PDF  73 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32WB09XE Datasheet(HTML) 14 Page - STMicroelectronics

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3.9
Reset management
The STM3WB09xE offers two different resets:
•
The PORESETn: this reset is provided by the low-power management unit (LPMU) analog block and
corresponds to a POR or PDR root cause. It is linked to power voltage ramp-up or ramp-down. This reset
impacts all resources of the STM3WB09xE. The exit from Shutdown mode is equivalent to a POR and thus
generates a PORESETn. The PORESETn signal is active when the power supply of the device is below a
threshold value or when the regulator does not provide the target voltage.
•
The PADRESETn (system reset): this reset is built through several sources:
–
PORESETn
–
Reset due to the watchdog
The STM3WB09xE device embeds a watchdog timer, which may be used to recover from software
crashes
–
Reset due to CPU Lockup
The Cortex®-M0+ generates a lockup to indicate the core is in the lock-up state resulting from an
unrecoverable exception. The lock-up reset is masked if a debugger is connected to the Cortex®-
M0+
–
Software system reset
The system reset request is generated by the debug circuitry of the Cortex®-M0+. The debugger sets
the SYSRESETREQ bit of the application interrupt and reset control register (AIRCR). This system
reset request through the AIRCR can also be done by the embedded software (into the hardfault
handler for instance)
–
Reset from the RSTN external pin
The RSTN pin toggles to inform that a reset has occurred
This PADRESETn resets all resources of the STM3WB09xE, except:
•
Debug features
•
Flash controller key management
•
RTC timer
•
Power controller unit
•
Part of the RCC registers
The pulse generator guarantees a minimum reset pulse duration of 20 μs for each internal reset source. In case
of reset from the RSTN external pad, the reset pulse is generated when the pad is asserted low.
3.10
Operating modes
Several operating modes are defined for the STM3WB09xE:
•
Run mode
•
Deepstop mode
•
Shutdown mode
Table 4. Relationship between the low-power modes and functional blocks
Mode
Shutdown
Deepstop
Idle
Run
CPU
OFF
OFF
OFF
ON
Flash
OFF
OFF
ON
ON
RAM
OFF
ON/OFF granularity 12
Kbytes
ON/OFF
ON/OFF
Radio
OFF
OFF
ON/OFF
ON/OFF
Supply system
OFF
OFF
ON ( DC-DC ON/
OFF)
ON ( DC-DC ON/
OFF)
Register retention
OFF
ON
ON
ON
HS clock
OFF
OFF
ON
ON
LS clock
OFF
ON/OFF
ON
ON
STM32WB09xE
Functional overview
DS14210 - Rev 6
page 14/73



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