STM32WB09XE datasheet(16/73 Pages) STMICROELECTRONICS

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All GPIOs can wake up the system

At wakeup, all the hardware resources located in the digital power domain that are OFF during Deepstop mode,

are reset. The CPU reboots. The wakeup reason is visible in the register of the power controller.

3.10.3

Shutdown mode

The Shutdown mode is the least power consuming mode.

The conditions to enter Shutdown mode are the same conditions needed to enter Deepstop mode except that the

LPMS bit of the power controller unit is 1.

In Shutdown mode, the STM3WB09xE is in ultra-low power consumption: all voltage regulators, clocks and the

RF interface are not powered. The STM3WB09xE can enter shutdown mode by internal software sequence. The

only way to exit shutdown mode is by asserting and deasserting the RSTN pin or through a configurable pulse on

PB0 pin.

In Shutdown mode:

•

The system is powered down as both the regulators are OFF

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The VDDIO power domain is ON

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All the clocks are OFF, LSI and LSE are OFF

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The I/Os pull-up and pull-down can be controlled during Shutdown mode, depending on the software

configuration

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The only wakeup source is a low pulse on the RSTN pin or a configurable pulse on PB0 pin

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The exit from Shutdown is similar to a POR startup. The PDR feature can be enabled or disabled during

Shutdown

3.11

Clock management

Three different clock sources may be used to drive the system clock of the STM3WB09xE:

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HSI: high speed internal 64 MHz RC oscillator

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PLL64M: 64 MHz PLL clock

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HSE: high speed 32 MHz external crystal

The STM3WB09xE has also a low-speed clock tree used by some timers in the radio, RTC, IWDG and LPUART.

Three different clock sources can be used for this low-speed clock tree:

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Low-speed internal (LSI): low-speed and low drift internal RC with a fixed frequency between 24 kHz and

49 kHz depending on the sample

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Low-speed external (LSE) from:

–

An external crystal 32.768 kHz

–

A single-ended 32.738 kHz input signal

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A 32 kHz clock obtained by dividing HSI or HSE. In this case, the slow clock is not available in Deepstop

low-power mode

By default, after a system reset, all low-speed sources are OFF.

Both the activation and the selection of the slow clock are relevant during the Deepstop mode and at wakeup as

slow clock generates a clock for the timers involved in wakeup event generation.

The HSI and the PLL64M clocks are provided by the same analog block called RC64MPLL. The 64 MHz clock

output by this block can be:

•

A non-accurate clock when no external XO provides an input clock to this block (HSI)

•

An accurate clock when the external XO provides the 32 MHz and once its internal PLL is locked (PLL64M)

After reset, the CLK_SYS is divided by four to provide a 16 MHz to the whole system (CPU, DMA, memories and

peripherals).

STM32WB09xE

Functional overview

DS14210 - Rev 6

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