STM32WB09XE datasheet(20/73 Pages) STMICROELECTRONICS

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3.17.2

Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from the LS clock

and it can operate in Deepstop mode. It can also be used as a watchdog to reset the device when a problem

occurs.

3.17.3

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It

features:

•

A 24-bit down counter

•

Autoreload capability

•

Maskable system interrupt generation when the counter reaches 0

3.18

Real-time clock (RTC)

The RTC is an independent BCD timer/counter. The RTC provides a time of day/clock/calendar with

programmable alarm interrupt. RTC includes also a periodic programmable wakeup flag with interrupt capability.

The RTC provides an automatic wakeup to manage all low power modes.

Two 32-bit registers contain seconds, minutes, hours (12- or 24-hour format), day (day of week), date (day of

month), month, and year, expressed in binary coded decimal format (BCD). The sub-second value is also

available in binary format. Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed

automatically. Daylight saving time compensation can also be performed. Additional 32-bit registers contain the

programmable alarm sub seconds, seconds, minutes, hours, day, and date.

A digital calibration circuit with 0.95 ppm resolution is available to compensate for quartz crystal inaccuracy. After

power-on reset, all RTC registers are protected against possible parasitic write accesses. As long as the supply

voltage remains in the operating range, the RTC never stops, regardless of the device status (Run mode, low-

power mode or under system reset). The RTC counter does not freeze when CPU is halted by a debugger.

3.19

Inter-integrated circuit interface (I2C)

The STM3WB09xE embeds ONE I2C. The I2C bus interface handles communications between the

microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.

The I2C peripheral supports:

•

I2C bus specification and user manual rev. 5 compatibilities:

–

Target and controller modes

–

Multicontroller capability

–

Standard-mode (Sm), with a bitrate up to 100 Kbit/s

–

Fast-mode (Fm), with a bitrate up to 400 Kbit/s

–

Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output driver I/Os

–

7-bit and 10-bit addressing mode

–

Multiple 7-bit target addresses (2 addresses, 1 with configurable mask)

–

All 7-bit address acknowledge mode

–

General call

–

Programmable setup and hold times

–

Easy to use event management

–

Optional clock stretching

–

Software reset

•

System management bus (SMBus) specification rev 2.0 compatibility:

–

Hardware PEC (packet error checking) generation and verification with ACK control

–

Address resolution protocol (ARP) support

–

Host and device support

–

SMBus alert

–

Timeouts and idle condition detection

•

Power system management protocol (PMBusTM) specification rev 1.1 compatibility

STM32WB09xE

Functional overview

DS14210 - Rev 6

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