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STM32F103XC Datasheet(PDF) 58 Page - STMicroelectronics

Part # STM32F103XC
Description  Performance line, ARM-based 32-bit MCU with up to 512 KB Flash, USB, CAN, 11 timers, 3 ADCs and 13 communication interfaces
PDF  118 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F103XC Datasheet(HTML) 58 Page - STMicroelectronics

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Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
58/118
5.3.10
FSMC characteristics
All the timing characteristics are relative to the FSMC_CLK signal for synchronous
SRAM/NOR Flash memory accesses.
Figure 22.
Asynchronous non-multiplexed SRAM/NOR write timings
1.
Mode 2/B, C and D only.
Table 30.
Asynchronous non-multiplexed SRAM/NOR write timings(1)
1.
TBD = to be determined.
VDD_IO = V and CL = 15 pF
Symbol
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
TBD
TBD
t
CK/ns
tv(WEN_NE)
FSMC_NEx low to FSMC_NWE low
TBD
TBD
t
CK/ns
tw(NWE)
FSMC_NWE low time
TBD
TBD
t
CK/ns
th(NE_NWE)
FSMC_NWE high to FSMC_NE high hold time
TBD
t
CK/ns
tv(A_NE)
FSMC_NEx low to FSMC_A valid
TBD
ns
th(A_NWE)
Address hold time after FSMC_NWE high
TBD
t
CK/ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
TBD
ns
th(BL_NWE)
FSMC_BL hold time after FSMC_NWE high
TBD
t
CK/ns
tv(Data_NE)
FSMC_NEx low to Data valid
TBD
t
CK/ns
th(Data_NWE)
Data hold time after FSMC_NWE high
TBD
t
CK/ns
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
TBD
t
CK/ns
tw(NADV)
FSMC_NADV low time
TBD
t
CK/ns
NBL
Data
FSMC_NEx
FSMC_NBL[3:0]
FSMC_D[15:0]
tv(BL_NE)
th(Data_NWE)
FSMC_NOE
Address
FSMC_A[25:0]
tv(A_NE)
tw(NWE)
FSMC_NWE
tv(NWE_NE)
t h(NE_NWE)
th(A_NWE)
th(BL_NWE)
tv(Data_NE)
tw(NE)
ai14990
FSMC_NADV(1)
t v(NADV_NE)
tw(NADV)



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