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STM32F103XC Datasheet(PDF) 99 Page - STMicroelectronics

Part # STM32F103XC
Description  Performance line, ARM-based 32-bit MCU with up to 512 KB Flash, USB, CAN, 11 timers, 3 ADCs and 13 communication interfaces
PDF  118 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F103XC Datasheet(HTML) 99 Page - STMicroelectronics

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STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
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5.3.18
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 57 are derived from tests
performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 9.
Note:
It is recommended to perform a calibration after each power-up.
Table 57.
ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
ADC power supply
2.4
3.6
V
VREF+
Positive reference voltage
2.4
VDDA
V
fADC
ADC clock frequency
0.6
14
MHz
fS
(1)
Sampling rate
0.05
1
MHz
fTRIG
(1)
External trigger frequency
fADC = 14 MHz
823
kHz
17
1/fADC
VAIN
Conversion voltage range(2)
0 (VSSA or VREF-
tied to ground)
VREF+
V
RAIN
(1)
External input impedance
See Equation 1 and Table 58
k
Ω
RADC
(1)
Sampling switch resistance
1
k
Ω
CADC
(1)
Internal sample and hold
capacitor
5pF
tCAL
(1)
Calibration time
fADC = 14 MHz
5.9
µs
83
1/fADC
tlat
(1)
Injection trigger conversion
latency
fADC = 14 MHz
0.214
µs
3(3)
1/fADC
tlatr
(1)
Regular trigger conversion
latency
fADC = 14 MHz
0.143
µs
2(3)
1/fADC
tS
(1)
Sampling time
fADC = 14 MHz
0.107
17.1
µs
1.5
239.5
1/fADC
tSTAB
(1)
Power-up time
0
0
1
µs
tCONV
(1)
Total conversion time
(including sampling time)
fADC = 14 MHz
118
µs
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1.
Guaranteed by design, not tested in production.
2.
VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 3: Pin descriptions for further details.
3.
For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 57.



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