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STM32F103XC Datasheet(PDF) 31 Page - STMicroelectronics |
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STM32F103XC Datasheet(HTML) 31 Page - STMicroelectronics |
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31 / 118 page ![]() STM32F103xC, STM32F103xD, STM32F103xE Pin descriptions 31/118 F6 --- 131 VDD_11 S B7 --- 132 PG15 I/O A7 A7 55 89 133 PB3/JTDO I/O FT JTDO PB3/TRACESWO JTDO SPI3_SCK/I2S3_CK/ TIM2_CH2 / SPI1_SCK A6 A6 56 90 134 PB4/JNTRST I/O FT JNTRST PB4/SPI3_MISO TIM3_CH1 / SPI1_MISO B6 C5 57 91 135 PB5 I/O PB5 I2C1_SMBAl/ SPI3_MOSI/I2S3_SD TIM3_CH2 / SPI1_MOSI C6 B5 58 92 136 PB6 I/O FT PB6 I2C1_SCL(6)/ TIM4_CH1(6) USART1_TX D6 A5 59 93 137 PB7 I/O FT PB7 I2C1_SDA(6)/ FSMC_NADV/ TIM4_CH2(6) USART1_RX D5 D5 60 94 138 BOOT0 I BOOT0 C5 B4 61 95 139 PB8 I/O FT PB8 TIM4_CH3(6)/SDIO_D4 I2C1_SCL/ CANRX B5 A4 62 96 140 PB9 I/O FT PB9 TIM4_CH4(6)/SDIO_D5 I2C1_SDA / CANTX A5 D4 - 97 141 PE0 I/O FT PE0 TIM4_ETR FSMC_NBL0 A4 C4 - 98 142 PE1 I/O FT PE1 FSMC_NBL1 E5 E5 63 99 143 VSS_3 SVSS_3 F5 F5 64 100 144 VDD_3 SVDD_3 1. I = input, O = output, S = supply, HiZ = high impedance. 2. FT = 5 V tolerant. 3. Function availability depends on the chosen device. 4. PC13, PC14 and PC15 are supplied through the power switch, and so their use in output mode is limited: they can be used only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time. 5. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 6. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100/BGA100 and LQFP144/BGA144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. Table 4. Pin definitions (continued) Pins Pin name Main function(3) (after reset) Alternate functions Default Remap |
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