STM32F103XC datasheet(91/118 Pages) STMICROELECTRONICS

91 / 118 page

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

91/118

I2S - SPI characteristics

Unless otherwise specified, the parameters given in Table 51 for SPI or in Table 52 for I2S

are derived from tests performed under ambient temperature, fPCLKx frequency and VDD

supply voltage conditions summarized in Table 9.

Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).

Table 51.

SPI characteristics(1) (2)

Symbol

Parameter

Conditions

Min

Max

Unit

fSCK

1/tc(SCK)

SPI clock frequency

Master mode

MHz

Slave mode

tr(SCK)

tf(SCK)

SPI clock rise and fall

time

Capacitive load: C = 30 pF

tsu(NSS)

(3)

NSS setup time

Slave mode

tC(SCK)

th(NSS)

(3)

NSS hold time

Slave mode

0.5tC(SCK)

tw(SCKH)

(3)

tw(SCKL)

(3)

SCK high and low time

Master mode, fPCLK = 36 MHz, presc = 4

tsu(MI)

(3)

tsu(SI)

(3)

Data input setup time

Master mode

Slave mode

th(MI)

(3)

th(SI)

(3)

Data input hold time

Master mode, fPCLK = 36 MHz, presc = 4

Slave mode, fPCLK = 36 MHz, presc = 4

Master mode, fPCLK = TBD

TBD(4)

Slave mode, fPCLK = TBD

TBD(4)

ta(SO)

(3)(5)

Data output access time

Slave mode, fPCLK = 36 MHz, presc = 4

Slave mode, fPCLK = TBD

TBD

tdis(SO)

(3)(6)

Data output disable time Slave mode

TBD

tv(SO)

(3)(1)

Data output valid time

Slave mode (after enable edge),

fPCLK = 36 MHz, presc = 4

fPCLK = TBD

TBD

tv(MO)

(3)(1)

Data output valid time

Master mode (after enable edge),

fPCLK = 36 MHz, presc = 4

fPCLK = TBD

TBD

th(SO)

(3)

Data output hold time

Slave mode (after enable edge)

th(MO)

(3)

Master mode (after enable edge)

TBD = to be determined.

Remapped SPI1 characteristics to be determined.

Values based on design simulation and/or characterization results, and not tested in production.

Depends on fPCLK. For example, if fPCLK= 8MHz, then tPCLK = 1/fPLCLK =125 ns and tv(MO) = 255 ns.

Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z

STM32F103XC Datasheet(PDF) 91 Page - STMicroelectronics

STM32F103XC Datasheet(HTML) 91 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL