AS7058 datasheet(28/199 Pages) AMSOSRAM

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AS7058

Functional description

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For applications requiring only one signal path to be active, one of the two channels can

certainly be powered down via simple register control to reduce overall system power

consumption. Each PPG Modulator signal path supports seven full-scale range settings of

1 µA, 2 µA, 4 µA, 8 µA, 16 µA, 32 µA, and 64 µA which can be configured in register

PPGMOD1_IOS_FS and PPGMOD2_IOS_FS for each ADC independently. In addition to the

full-scale settings both modulators have additional configuration registers PPG_SINC_CFGA,

PPG_SINC_CFGB and PPG_SINC_CFGC which allow the configuration of the decimation

filters and filter order to control the desired integrations times which are the determining factor

for signal integrity as well as noise behavior for the target application.

Each PPG signal path also includes an 8-bit offset current DAC for extending the optical

dynamic range by sourcing some of the exposure current to the offset DAC. This feature helps

to avoid the saturation of the ADC under high ambient light exposure. The current of the offset

DAC can be directly controlled via a dedicated registers IOS_PPG1_SUBx and

IOS_PPG2_SUBx for each subsample and each modulator separately. This allows engineers

to utilize their own offset compensations algorithms running on the host signal-processing unit.

However, in case customers do not have an algorithm in place, AS7058 features also an

Advanced Automatic Offset Cancellation (AAOC) function which is also shown in Figure 24

and Figure 25 which automatically controls the DC offset compensation DAC eliminating the

latency effect caused by I²C configuration of an external host MCU.

7.3.1

PPG signal processing overview

As indicated in the previous chapters and drawings, AS7058 supports various different post-

processing options. An overview of all options and device signal flow is shown in Figure 26.

Please note that the processing options shown in Figure 26 are for ADC Modulator 1 and ADC

Modulator 2 the same.

The output of each modulator is connected to the SINC filter block, which acts as down

sampling filter. It is possible to select between 4th and 5th filter order via register

PPG_SEL_ORDER as well as decimation rates between 16, 32, 64, 128 and 256 via register

PPG_SINC_DEC. In order to further improve SNR of the system there is an oversampling filter

function, which is part of the down sampling filter, that can be enabled via register

PPG_SINC_OVS. The three-bit register allows to enable 7 different oversampling filter ratios

from factor 2 up to 128. The oversampling filter function is disabled in default configuration.

Please mind that enabling the oversampling filter function the active ADC modulator time is

increased influencing power consumption with the benefit of better noise behavior. Once the

signal passed the SINC decimation and optional oversampling filter the PPG signal is feed into

a scaling block which converts the signal in to 20-bit unsigned signal. The next post-processing

block, which can be enabled via register MOVING_AVERAGE_ON is an on-chip moving

average filter.

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