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AS7058 Datasheet(PDF) 63 Page - ams-OSRAM AG

Part # AS7058
Description  IC for PPG, ECG and body impedance measurement
PDF  199 Pages
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Manufacturer  AMSOSRAM [ams-OSRAM AG]
Direct Link  https://ams-osram.com/
Logo AMSOSRAM - ams-OSRAM AG

AS7058 Datasheet(HTML) 63 Page - ams-OSRAM AG

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AS7058
Functional description
Datasheet • PUBLIC • Document Feedback
DS001077 • v2-00 • 2025-Sep-24
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7.10.3.4 I²C read
For reading data from the slave device, the master has to change the transfer direction. This
can be done either with a repeated START condition followed by the device-read address or
with a new transmission START followed by the device-read address when the bus is in an
IDLE state. The device-read address is always followed by the first register byte transmitted
from the slave. In Read mode, any number of subsequent register bytes can be read from the
slave. The word address is incremented internally.
Figure 55: I²C random read format
Random Read and Sequential Read are combined formats. The repeated START condition is
used to change the direction after the data transfer from the master.
The word address transfer is initiated with a START condition issued by the master while the
bus is idle. The START condition is followed by the device-write address and the word
address.
To change the data direction, a repeated START condition is issued on the first SCL pulse
after the acknowledge bit of the word address transfer. After the reception of the device-read
address, the slave becomes the transmitter. In this state, the slave transmits register data
located by the previously received word address vector. The master responds to the data byte
with a “not-acknowledge” and issues a STOP condition on the bus.
Figure 56: I²C sequential read format
Sequential Read is the extended form of Random Read, as more than one register-data byte is
subsequently transferred. In contrast to the Random Read, an acknowledge from the master is
the response for the transferred register-data bytes for a sequential read.
A
DW
S
WA
A Sr
P
DR
A
data
N
RA++
A
DW
S
WA
A Sr
DR
A
data 1
A
data 2
A
...
data n
P
N
RA++
RA++
RA++



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