R5F5671CDDLE datasheet(148/179 Pages) RENESAS

148 / 179 page

R01DS0373EJ0120 Rev.1.20

Page 148 of 179

Sep 30, 2024

RX671 Group

2. Electrical Characteristics

Note:

tIICcyc: RIIC internal reference clock (IICφ) cycle

Note 1. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by

the setting ICFER.NFE = 1.

Note 2. Cb is the total capacitance of the bus lines.

Figure 2.85

RIIC Bus Interface Input/Output Timing

Table 2.47

RIIC Timing (2)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr

Item

Symbol

Min.*1

Max.

Unit

Test

Conditions

RIIC

(Fast-mode+)

ICFER.FMPE = 1

SCL input cycle time

tSCL

6(12) × tIICcyc + 240

—

Figure 2.85

SCL input high pulse width

tSCLH

3(6) × tIICcyc + 120

—

SCL input low pulse width

tSCLL

3(6) × tIICcyc + 120

—

SCL, SDA input rise time

tSr

—

120

SCL, SDA input fall time

tSf

—

120

SCL, SDA input spike pulse removal time

tSP

01(4) × tIICcyc

SDA input bus free time

tBUF

3(6) × tIICcyc + 120

—

START condition input hold time

tSTAH

tIICcyc + 120

—

Repeated START condition input setup

time

tSTAS

120

—

STOP condition input setup time

tSTOS

120

—

Data input setup time

tSDAS

tIICcyc + 20

—

Data input hold time

tSDAH

0—

SCL, SDA capacitive load

Cb*2

—

550

SDA0 to SDA2

SCL0 to SCL2

VIH

VIL

tSTAH

tSCLH

tSCLL

P*1

S*1

tSf

tSr

tSCL

tSDAH

tSDAS

tSTAS

tSP

tSTOS

P*1

tBUF

Test conditions

VIH = 0.7 × VCC, VIL = 0.3 × VCC

VOL = 0.6 V, IOL = 6 mA

Sr*1

Note 1. S, P, and Sr indicate the following conditions.

S: START condition

P: STOP condition

Sr: Repeated START condition

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