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R5F5671CDDLE Datasheet(PDF) 149 Page - Renesas Technology Corp |
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R5F5671CDDLE Datasheet(HTML) 149 Page - Renesas Technology Corp |
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149 / 179 page  R01DS0373EJ0120 Rev.1.20 Page 149 of 179 Sep 30, 2024 RX671 Group 2. Electrical Characteristics 2.4.7.16 RIICHS Table 2.48 RIICHS Timing (1) Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr Item Symbol Min.*1 Max. Unit Test Conditions RIICHS (Standard-mode, SMBus) ICFER.FMPE = 0 SCLHS input cycle time tSCL 10(18) × tIICcyc + 1300 — ns Figure 2.86 SCLHS input high pulse width tSCLH 5(9) × tIICcyc + 300 — ns SCLHS input low pulse width tSCLL 5(9) × tIICcyc + 300 — ns SCLHS, SDAHS input rise time tSr — 1000 ns SCLHS, SDAHS input fall time tSf — 300 ns SCLHS, SDAHS input spike pulse removal time tSP 01(4) × tIICcyc ns SDAHS input bus free time tBUF 5(9) × tIICcyc + 300 — ns START condition input hold time tSTAH tIICcyc + 300 — ns Repeated START condition input setup time tSTAS 1000 — ns STOP condition input setup time tSTOS 1000 — ns Data input setup time tSDAS tIICcyc + 50 — ns Data input hold time tSDAH 0— ns SCLHS, SDAHS capacitive load Cb*2 — 400 pF RIICHS (Fast-mode) ICFER.FMPE = 0 SCLHS input cycle time tSCL 10(18) × tIICcyc + 600 — ns SCLHS input high pulse width tSCLH 5(9) × tIICcyc + 300 — ns SCLHS input low pulse width tSCLL 5(9) × tIICcyc + 300 — ns SCLHS, SDAHS input rise time tSr 20 × (External pull-up voltage/5.5V) 300 ns SCLHS, SDAHS input fall time tSf 20 × (External pull-up voltage/5.5V) 300 ns SCLHS, SDAHS input spike pulse removal time tSP 01(4) × tIICcyc ns SDAHS input bus free time tBUF 5(9) × tIICcyc + 300 — ns START condition input hold time tSTAH tIICcyc + 300 — ns Repeated START condition input setup time tSTAS 300 — ns STOP condition input setup time tSTOS 300 — ns Data input setup time tSDAS tIICcyc + 50 — ns Data input hold time tSDAH 0— ns SCLHS, SDAHS capacitive load Cb*2 — 400 pF RIICHS (Fast-mode+) ICFER.FMPE = 1 SCLHS input cycle time tSCL 10(18) × tIICcyc + 240 — ns SCLHS input high pulse width tSCLH 5(9) × tIICcyc + 120 — ns SCLHS input low pulse width tSCLL 5(9) × tIICcyc + 120 — ns SCLHS, SDAHS input rise time tSr — 120 ns SCLHS, SDAHS input fall time tSf — 120 ns SCLHS, SDAHS input spike pulse removal time tSP 01(4) × tIICcyc ns SDAHS input bus free time tBUF 5(9) × tIICcyc + 120 — ns START condition input hold time tSTAH tIICcyc + 120 — ns Repeated START condition input setup time tSTAS 120 — ns STOP condition input setup time tSTOS 120 — ns Data input setup time tSDAS tIICcyc + 20 — ns Data input hold time tSDAH 0— ns SCLHS, SDAHS capacitive load Cb*2 — 550 pF |
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