R5F5671CDDLE datasheet(151/179 Pages) RENESAS

151 / 179 page

R01DS0373EJ0120 Rev.1.20

Page 151 of 179

Sep 30, 2024

RX671 Group

2. Electrical Characteristics

Note:

tIICcyc: RIICHS internal reference clock (IICφ) cycle

Note 1. The value within parentheses is applicable when the value of the ICICR.NF[3:0] bits is 0011b while the digital filter is enabled by

the setting ICICR.NFE = 1. Note that, in Hs-mode, the lower-order 2 bits of the NF[3:0] bits are ignored and the number of

stages in the digital filter is single.

Note 2. Cb is the total capacitance of the bus lines.

Figure 2.87

RIICHS Bus Interface Input/Output Timing (Hs-mode)

RIICHS

(Hs-mode)

ICFER.HSME

= 1

SCLHS output minimum high

pulse width

Cb = 400pF tSCLH(min)

—

120

233

ns Figure 2.87

Cb = 100pF

—

150

SCLHS output minimum low

pulse width

Cb = 400pF tSCLL(min)

—

320

Cb = 100pF

—

160

Table 2.49

RIICHS Timing (2) (2/2)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr

Item

Symbol

Min.*1

Typ.

Max.

Unit

Test

Conditions

SDAHS0

SCLHS0

tSfDA

tSrDA

tSTAH

tSTAS

tSDAH

tSDAS

tSTOS

tSfCL

tSCLH

tSCLL

tSrCL

0.3 × VCC

= MCS current source pull-up

= Rp resistor pull-up

0.7 × VCC

0.3 × VCC

0.7 × VCC

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