RIVA128ZX datasheet(8/85 Pages) STMICROELECTRONICS

8 / 85 page

128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX

8/85

2.5

DEVICE ENABLE SIGNALS

2.6

DISPLAY INTERFACE

2.7

VIDEO DAC AND PLL ANALOG SIGNALS

2.8

POWER SUPPLY

Signal

I/O

Description

ROMCS#

Enables reads from an external 64Kx 8 or 32Kx8 ROM or Flash ROM. This signal is used

in conjunction with framebuffer data lines as described above in Section 2.3.

Signal

I/O

Description

SDA

I/O

Used for DDC2B+ monitor communication and interface to video decoder devices.

SCL

I/O

Used for DDC2B+ monitor communication and interface to video decoder devices.

VIDVSYNC

Vertical sync supplied to the display monitor. No buffering is required. In TV mode this sig-

nal supplies composite sync to an external PAL/NTSC encoder.

VIDHSYNC

Horizontal sync supplied to the display monitor. No buffering is required.

Signal

I/O

Description

RED,

GREEN,

BLUE

RGB display monitor outputs. These are software configur able to drive either a doubly ter-

minated or singly terminated 75

Ω load.

COMP

External compensation capacitor for the video DACs. This pin should be connected to

DACVDD via the compensation capacitor, see Figure 66, page 60.

RSET

A precision resistor placed between this pin and GND sets the full-scale video DAC cur-

rent, see Figure 66, page 60.

VREF

A capacitor should be placed between this pin and GND as shown in Figure 66, page 60.

XTALIN

A series resonant crystal is connected between these two points to provide the reference

clock for the internal MCLK and VCLK clock synthesizers, see Figure 66 and Table 20,

page 60. Alternately, an external LVTTL clock oscillator output may be driven into XTA-

LOUT, connecting XTALIN to GND. For designs supporting TV-out, XTALOUT should be

driven by a reference clock as described in Section 11.6, page 61.

XTALOUT

Signal

I/O

Description

DACVDD

Analog power supply for the video DACs.

PLLVDD

Analog power supply for all clock synthesizers.

VDD

Digital power supply.

GND

Ground.

MPCLAMP

MPCLAMP is connected to +5V to protect the 3.3V RIVA128ZX from external devices

which will potentially drive 5V signal levels onto the Video Port input pins.

HOSTVDD

HOSTVDD is connected to the Vddq 3.3 pins on the AGP connector. This is the supply

voltage for the I/O buffers and is isolated from the core VDD. On AGP designs these pins

are also connected to the HOSTCLAMP pins. On PCI designs they are connected to the

3.3V supply.

HOSTCLAMP

HOSTCLAMP is the supply signalling rail protection for the host interface. In AGP designs

these signals are connected to Vddq 3.3. For PCI designs they are connected to the I/O

power pins (V(I/O)).

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