RIVA128ZX datasheet(56/85 Pages) STMICROELECTRONICS

56 / 85 page

128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX

56/85

[2]

RAM Type

0 = 16Mbit, 2 or 4 internal bank SGRAM or 16Mbit SDRAM. The BIOS should test the memory to

determine whether it supports 2 or 4 internal banks.

1 = 8Mbit, 2 internal bank SGRAM.

Although a 10K

Ω resistor is used to strap the default state of this bit in RIVA 128 and RIVA128ZX

reference designs, it is ignored by the video BIOS which auto-detects the memory type and con-

figures the RIVA128ZX appropriately.

[1]

Sub-Vendor. This bit indicates whether the PCI Subsystem Vendor field is located in the system

motherboard BIOS or adapter card VGA BIOS. If the Subsystem Vendor field is located in the sys-

tem BIOS it must be written by the system BIOS to the PCI configuration space prior to running

any PnP code.

0 = System BIOS (Subsystem Vendor ID and Subsystem ID set to 0x0000)

1 = Adapter card VGA BIOS (Subsystem Vendor ID and Subsystem ID read from ROM BIOS at

location 0x54 - 0x57)

[0]

Bus Speed. This bit indicates the value returned in the 66MHz bit in the PCI Configuration regis-

ters.

0 = RIVA128ZX PCI interface is 33MHz

1 = RIVA128ZX is 66MHz capable

The following example configuration is shown in Figure 65:

• Subsystem Vendor ID initialized to 0 and writeable by system BIOS (see Appendix A, page 76)

• 8Mbit, 2 internal bank, SGRAM

• 128-bit framebuffer interface

• AGP 2X mode enabled including 66MHz PCI 2.1 compliant subset

• Using 13.5000MHz crystal

• TV output mode is NTSC

Figure 65.

Example motherboard configuration

10K

Ω

RIVA128ZX

FBA[1

]

FBA[2]

FBA[3]

SGRAM

array

VDD (3.3V)

FBA[4]

FBA[5]

FBA[8]

FBA[6]

FBA[7]

FBA[0

]

FBA[9]

FBA[10]

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