RIVA128ZX datasheet(32/85 Pages) STMICROELECTRONICS

32 / 85 page

128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX

32/85

6.2

SGRAM INTERFACE

Signal changes between RIVA 128 and RIVA128ZX

The extra address signal (FBA[10]) required to address 16Mbit SGRAM devices was defined on RIVA 128

and was connected to pin 30 of the SGRAM in the RIVA 128 Reference Design schematics. This pin is a

N/C on 8Mbit memory devices and it was also N/C on RIVA 128. For 8MByte designs using 8Mbit devices;

FBCS0# drives the chip selects for the first external bank of memory and FBCS1# drives the second ex-

ternal bank.

The ROM BIOS implements code which automatically detects the configuration and memory type. If a mix-

ture of 4-internal bank and 2-internal bank 16Mbit devices are used (e.g. 2 soldered down and 2 added by

an end user as an SO-DIMM) then RIVA128ZX will program those devices and operate itself as 2-internal

bank. There is no support for mixed 16Mbit and 8Mbit memories (i.e. there is no 6MByte mode) nor is there

support for 16MByte using eight 16Mbit devices. The upgrade path from two devices to four devices has

also been changed to better accommodate board layout for SO-DIMMs. As shown in Figure 29, the first

two memories installed are on the left side of the chip and the upgrade is on the right hand side. This is

different to RIVA 128 which populated the top two chips first and then populated the lower (far left and far

right) memories as the upgrade. Both forms of 64-bit bus are supported in RIVA128ZX and the data paths

populated are determined by the BIOS during its boot memory detection sequence.

Figure 29.

Upgrade from 64-bit 4MByte to 128-bit 8MByte SGRAM via SO-DIMM

RIVA128ZX

FBD[31:0]

FBD[95:64]

Bank 2

512K

x32

FBD[63:32]

FBD[127:96]

Upgrade to

8MByte via

SO-DIMM

First two

memories

installed

Bank 0

512K

x32

Bank 1

512K

x32

Bank 3

512K

x32

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