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RIVA128ZX Datasheet(PDF) 40 Page - STMicroelectronics |
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RIVA128ZX Datasheet(HTML) 40 Page - STMicroelectronics |
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40 / 85 page  128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX 40/85 Figure 40. SDRAM/SGRAM read to precharge, read latency of three NOTE 1 FBDQM is active (low) Figure 41. SDRAM/SGRAM Write to Precharge Figure 42. SDRAM/SGRAM Active to Read or Write Table 12. SDRAM/SGRAM timing parameters Symbol Parameter Min. Max. Unit Notes tCS FBCSx, FBRAS#, FBCAS#, FBWE#, FBDQM setup time 3ns tCH FBCSx, FBRAS#, FBCAS#, FBWE#, FBDQM hold time 1ns tMTC Load Mode register command to command 2 tCK tRAS Active to Precharge command period 7 tCK tRC Active to Active command period 10 tCK tRCD Active to Read or Write delay 3 tCK precharge nop nop active bank(s) bank, data n tRP read bank, FBCLKx Command FBA[10:0] FBD[63:0] col n row write nop nop precharge nop nop active bank(s) row tRP tWR bank, col n write data n write data n+1 FBCLKx FBDQM# Command FBA[10:0] FBD[63:0] active nop nop tRCD read or write FBCLKx Command |
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