RIVA128ZX datasheet(39/85 Pages) STMICROELECTRONICS

39 / 85 page

128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX

39/85

Table 11.

SDRAM/SGRAM I/O timing parameters

Figure 37.

SDRAM/SGRAM random write cycles within a page

NOTE

Covers either successive writes to the active row in a given bank or to the active rows in different banks. FBDQM is active

(low).

Figure 38.

SDRAM/SGRAM write to read cycle

NOTE

A read latency of 2 is shown for illustration

Figure 39.

SDRAM/SGRAM read to precharge, read latency of two

NOTE

FBDQM is active (low)

Symbol

Parameter

Min.

Max.

Unit

Notes

tHZ

Data out high impedance time

tDS

Write data setup time

write

data n

data a

data x

data m

bank, col n

bank, col a

bank, col x

bank, col m

FBCLKx

Command

FBA[10:0]

FBD[63:0]

write

nop

read

nop

bank,

col n

bank,

col b

write

data n

write

data n

read

data b

FBCLKx

Command

FBA[10:0]

FBD[63:0]

nop

active

bank(s)

bank,row

data n

tRP

read

precharge

nop

bank, col n

FBCLKx

Command

FBA[10:0]

FBD[63:0]

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