NRF52820-QDAA-R datasheet(129/437 Pages) NORDIC

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Peripherals

Note: The CPU can read the LATCH register at any time to check if a SENSE condition has been

met on any of the GPIO pins. This is still valid if that condition is no longer met at the time the CPU

queries the LATCH register. This mechanism will work even if the LDETECT signal is not used as the

DETECT signal.

The LDETECT signal is by default not connected to the GPIO port's DETECT signal, but via the DETECTMODE

the LDETECT signal. See GPIO port and the GPIO pin details on page 128. The following figure illustrates

the DETECT signal behavior for these two alternatives.

PIN0.DETECT

PIN1.DETECT

PIN31.DETECT

DETECT

(Default mode)

DETECT

(LDETECT mode)

LATCH.0

LATCH.1

LATCH.31

Figure 43: DETECT signal behavior

A GPIO pin input buffer can be disconnected from the pin to enable power savings when the pin is not

used as an input, see GPIO port and the GPIO pin details on page 128. Input buffers must be connected

to get a valid input value in the IN register, and for the sense mechanism to get access to the pin.

Other peripherals in the system can connect to GPIO pins and override their output value and

configuration, or read their analog or digital input value. See GPIO port and the GPIO pin details on page

128.

Selected pins also support analog input signals, see ANAIN in GPIO port and the GPIO pin details on page

128. The assignment of the analog pins can be found in Pin assignments on page 415.

Note: When a pin is configured as digital input, increased current consumption occurs when the

input voltage is between VIL and VIH. It is good practice to ensure that the external circuitry does

not drive that pin to levels between VIL and VIH for a long period of time.

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NRF52820-QDAA-R Datasheet(PDF) 129 Page - Nordic Semiconductor