NRF52820-QDAA-R datasheet(353/437 Pages) NORDIC

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Peripherals

The GPIOs used for each UART interface can be chosen from any GPIO on the device and are

independently configurable. This enables great flexibility in device pinout and efficient use of board space

and signal routing.

Note: The external crystal oscillator must be enabled to obtain sufficient clock accuracy for stable

communication. See CLOCK — Clock control on page 69 for more information.

6.25.1 EasyDMA

The UARTE implements EasyDMA for reading and writing to and from the RAM.

If the TXD.PTR and the RXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may result

in a HardFault or RAM corruption. See Memory on page 15 for more information about the different

memory regions.

The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the next RX/

TX transmission immediately after having received the RXSTARTED/TXSTARTED event.

The ENDRX and ENDTX events indicate that the EasyDMA is finished accessing the RX or TX buffer in RAM.

6.25.2 Transmission

The first step of a DMA transmission is storing bytes in the transmit buffer and configuring EasyDMA. This

is achieved by writing the initial address pointer to TXD.PTR, and the number of bytes in the RAM buffer to

TXD.MAXCNT. The UARTE transmission is started by triggering the STARTTX task.

After each byte has been sent over the TXD line, a TXDRDY event will be generated.

When all bytes in the TXD buffer, as specified in the TXD.MAXCNT register, have been transmitted, the

UARTE transmission will end automatically and an ENDTX event will be generated.

A UARTE transmission sequence is stopped by triggering the STOPTX task. A TXSTOPPED event will be

generated when the UARTE transmitter has stopped.

If the ENDTX event has not already been generated when the UARTE transmitter has come to a stop, the

UARTE will generate the ENDTX event explicitly even though all bytes in the TXD buffer, as specified in the

TXD.MAXCNT register, have not been transmitted.

If flow control is enabled through the HWFC field in the CONFIG register, a transmission will be

automatically suspended when CTS is deactivated and resumed when CTS is activated again, as shown in

the following figure. A byte that is in transmission when CTS is deactivated will be fully transmitted before

the transmission is suspended.

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NRF52820-QDAA-R Datasheet(PDF) 353 Page - Nordic Semiconductor