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ST20-C1 Datasheet(PDF) 102 Page - STMicroelectronics |
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ST20-C1 Datasheet(HTML) 102 Page - STMicroelectronics |
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102 / 205 page  102/205 ® divstep divide step Code: 21 F8 Description: Perform a step of an integer division to generate 4 bits of the quotient. Areg holds the positive divisor. Breg and Creg hold the non-negative dividend or partial remainder and the partial result. Before the first step, Breg holds the dividend and Creg must be 0. After performing divstep 8 times, Breg will hold the quotient and Creg the remainder. Definition: if (Areg > 0 and Breg ≥ 0 and Creg ≥ 0) { Breg ′← (Breg << 4) ∨ (part_div / Areg) Creg ′← part_div rem Areg } else { Breg ′← undefined Creg ′← undefined } where part_div = (Creg << 4) ∨ (Breg >> 28) – the value of part_div is calculated to unlimited precision Status Register: No effect. Comments: Secondar y instruction. Areg must be greater than zero. Breg and Creg must be not less than zero. See also: unsign section 4.4. |
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