ST20-C1 datasheet(20/205 Pages) STMICROELECTRONICS

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3.3 Registers

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An implementation of the ST20-C1 core may include a

mechanism to accelerate access to local work space without changing the

programmer’s model of how the work space operates or impacting either the excellent

code density or low interrupt latency associated with a stack-based instruction set.

3.3

Registers

This section introduces the ST20-C1 core registers that are visible to the programmer.

Seven registers, known as process state registers, define the local state of the

executing process. These registers are preserved through exceptions. One other

tions. All registers are 32-bit. Each instruction explicitly refers to specific registers , as

described in the instruction definitions .

The state of an executing process at any instant is defined b y the contents of the

machine registers listed in Table 3.1. The registers are illustrated in Figure 3.4 and

described in the rest of this section.

Figure 3.4 Register set

Description

Areg

Evaluation stack register A

Breg

Evaluation stack register B

Creg

Evaluation stack register C

Iptr

Instruction pointer register, pointing to the next instruction to be executed

Status

Status register

Wptr

Work space pointer, pointing to the stack of the currently executing process

Tdesc

Task descriptor

IOreg

Input and output register

Table 3.1 Processor registers

Iptr

Areg

Breg

Creg

IOReg

Tdesc

Wptr

Evaluation Stack

Memory

Program

Code

Local

Program

Data

offset

base

Status

Task Descriptor

Instruction Pointer

Workspace Pointer

ST20-C1 Core

Task Control

Block

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