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EMC326SP16AJS-90LL Datasheet(PDF) 17 Page - Emerging Memory & Logic Solutions Inc

Part # EMC326SP16AJS-90LL
Description  2Mx16 bit CellularRAM
PDF  64 Pages
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Manufacturer  EMLSI [Emerging Memory & Logic Solutions Inc]
Direct Link  http://www.emlsi.com
Logo EMLSI - Emerging Memory & Logic Solutions Inc

EMC326SP16AJS-90LL Datasheet(HTML) 17 Page - Emerging Memory & Logic Solutions Inc

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EMC326SP16AJ
2Mx16 CellularRAM
17
Preliminary
Registers
Two user-accessible configuration registers define the device operation. The bus configuration register (BCR) defines how the Cellu-
larRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh
configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded
with default settings during power-up, and can be updated any time the devices are operating in a standby state. A DIDR provides
information on the device manufacturer, CellularRAM generation, and the specific device configuration. The DIDR is read-only.
Access Using CRE
The registers can be accessed using either a synchronous or an asynchronous operation when the control register enable (CRE) input
is HIGH. (See Figure 10 through 13) When CRE is LOW, a READ or WRITE operation will access the memory array. The configuration
register values are written via addresses A[20:0]. In an asynchronous WRITE, the values are latched into the configuration register on
the rising edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB# are “Don’t Care”. The BCR is accessed when A[19:18]
are 10b; the RCR is accessed when A[19:18] are 00b. The DIDR is read when A[19:18] are 01b. For reads, address inputs other than
A[19:18] are “Don’t Care”, and register bits 15:0 are output on DQ[15:0]. Immediately after performing a configuration register READ or
WRITE operation, reading the memory array is highly recommended.
Figure 10: Configuration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation
Note: 1. A[19:18] = 00b to load RCR, and 10b to load BCR.
Don’t Care
CE#
A[20:0]
OE#
WE#
LB#/UB#
DQ[15:0]
OPCODE
Address
A[19:18]1
(except A[19:18])
CRE
Initiate control register access
Data Valid
Write address bus value
tAVS
tCPH
Address
Select control register
tAVH
tAVS
tAVH
tCW
to control register
tWP
ADV#
tVP



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