EMC326SP16AJS-90LL datasheet(22/64 Pages) EMLSI

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EMC326SP16AJ

2Mx16 CellularRAM

Preliminary

Bus Configuration Register

The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit

contained in the RCR. Figure 16 describes the control bit BCR. At power-up, the BCR is set to 9D1Fh. The BCR is accessed with CRE

HIGH and A[19:18] = 10b, or through the register access software sequence with DQ = 0001h on the third cycle.

Figure 16: Bus Configuration Register Definition

Note: 1. Burst wrap and length apply to both READ and WRITE operations.

A[20]

A[19:18] A[17:16]

A15

A14

A13 A12 A11

A10

A5 A4

A2 A1 A0

19-18

17-16

Reserved

Select

Reserved

Operating

Mode

Initial

Latency

Counter

WAIT

Polarity

Reserved

WAIT

Configuration(WC)

Reserved Reserved

Drive

Strength

Burst

Wrap(BW)*

Burst

Length(BL)*

BCR[14]

Initial Access Latency

BCR[3]

Burst Wrap (Note 1)

Variable (default)

Burst wraps within the burst length

Fixed

Burst no wrap (default)

BCR[5] BCR[4] Drive Strength

BCR[13] BCR[12] BCR[11]

Latency Counter

Full

Code 8

1/2 (default)

Code 1 - Reserved

1/4

Code 2

Reserved

Code 3 (default)

Code 4

Code 5

BCR[8]

WAIT Configuration

Code 6

Asserted during delay

Code 7 - Reserved

Asserted one data before delay(default)

BCR[10]

WAIT Polarity

Active LOW

Active HIGH (default)

BCR[15]

Operating Mode

Synchronous burst access mode

BCR[2] BCR[1] BCR[0] Burst Length (Note 1)

Asynchronous access mode (default)

4 words

8 words

BCR[19] BCR[18] Register Select

16 words

Select RCR

32 words

Select BCR

Continuous burst (default)

Select DIDR

Others

Reserved

All must be set to “0” Must be set to “0”

Must be set to “0”

EMC326SP16AJS-90LL Datasheet(PDF) 22 Page - Emerging Memory & Logic Solutions Inc

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