EMC326SP16AJS-90LL datasheet(34/64 Pages) EMLSI

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EMC326SP16AJ

2Mx16 CellularRAM

Preliminary

Table 16: Burst WRITE Cycle Timing Requirements

Note:

1. tAS required if tCSP > 20ns.

2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE#

HIGH, or b) CE# HIGH for longer than 15ns.

3. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2.

Parameter

Symbol

133MHz

104MHz

83MHZ

Unit Notes

Min

Max

Min

Max

Min

Max

Address and ADV# LOW setup time

tAS

0-0

Address HOLD from ADV# HIGH(fixed latency)

tAVH

2-2

CE# HIGH between subsequent burst or mixed mode

operations

tCBPH

5-5

Maximum CE# pulse width

tCEM

-4-

µs

CE# LOW to WAIT valid

tCEW

7.517.517.5

Clock period

tCLK

7.5

9.62

CE# setup to CLK active edge

tCSP

2.5

Hold time from active CLK edge

tHD

1.5

Chip disable to WAIT High-Z output

tHZ

-7-

-8

CLK rise or fall time

tKHKL

1.2

1.6

1.8

Clock to WAIT valid

tKHTL

-5.5

CLK HIGH or LOW time

tKP

3-3

Setup time to activate CLK edge

tSP

2-3

EMC326SP16AJS-90LL Datasheet(PDF) 34 Page - Emerging Memory & Logic Solutions Inc

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