EMC326SP16AJS-90LL datasheet(31/64 Pages) EMLSI

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EMC326SP16AJ

2Mx16 CellularRAM

Preliminary

TIMING REQUIREMENTS

Table 13: Asynchronous READ Cycle Timing Requirements

All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b).

Note:

1. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2.

2. The Low-Z timings measure a 100mV transition away from the High-Z (VccQ/2) level toward either VOH or VOL.

3. Page mode enabled only.

4. Contact EMLSI for specific timing.

Parameter

Symbol

70ns

Unit

Note

Min

Max

Address access time

tAA

-70

ADV# access time

tAADV

-70

Page access time

tAPA

-20

Address hold from ADV# HIGH

tAVH

Address setup to ADV# HIGH

tAVS

LB#/UB# access time

tBA

-70

LB#/UB# disable to DQ High-Z output

tBHZ

-8

LB#/UB# enable to Low-Z output

tBLZ

Maximum CE# pulse width

tCEM

-4

µs

CE# LOW to WAIT valid

tCEW

17.5

Chip select access time

tCO

-70

CE# LOW to ADV# HIGH

tCVS

Chip disable to DQ and WAIT High-Z output

tHZ

-8

Chip enable to Low-Z output

tLZ

Output enable to valid output

tOE

-20

Output hold from address change

tOH

Output disable to DQ High-Z output

tOHZ

-8

Output enable to Low-Z output

tOLZ

Page READ cycle time

tPC

READ cycle time

tRC

ADV# pulse width LOW

tVP

EMC326SP16AJS-90LL Datasheet(PDF) 31 Page - Emerging Memory & Logic Solutions Inc

EMC326SP16AJS-90LL Datasheet(HTML) 31 Page - Emerging Memory & Logic Solutions Inc

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