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EMC326SP16AJS-90LL Datasheet(PDF) 32 Page - Emerging Memory & Logic Solutions Inc |
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EMC326SP16AJS-90LL Datasheet(HTML) 32 Page - Emerging Memory & Logic Solutions Inc |
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32 / 64 page  EMC326SP16AJ 2Mx16 CellularRAM 32 Preliminary Table 14: Burst READ Cycle Timing Requirements All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b). Note: 1. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. 2. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2. 3. The Low-Z timings measure a 100mV transition away from the High-Z (VccQ/2) level toward either VOH or VOL. Parameter Symbol 133MHz 104MHz 83MHZ Unit Note Min Max Min Max Min Max Address access time (fixed latency) tAA -70-70 -70 ns ADV# access time (fixed latency) tAADV -70-70 -70 ns Burst to READ access time (variable latency) tABA - 35.5 - 35.9 - 45 ns CLK to output delay tACLK - 5.5 -7 -9 ns Address hold from ADV# HIGH(fixed latency) tAVH 2 - 2- 2- ns Burst OE# LOW to output delay tBOE -20-20 -20 ns CE# HIGH between subsequent burst or mixed mode operations tCBPH 5 - 5- 6- ns 1 Maximum CE# pulse width tCEM - 4 -4 -4 µs 1 CE# or ADV# LOW to WAIT valid tCEW 17.517.517.5 ns CLK period tCLK 7.5 - 9.62 - 12 - ns Chip select access time (fixed latency) tCO -70-70 -70 ns CE# setup time to active CLK edge tCSP 2.5 - 3- 4- ns Hold time from active CLK edge tHD 1.5 - 2- 2- ns Chip disable to DQ and WAIT High-Z output tHZ - 7 -8 -8 ns 3 CLK rise or fall time tKHKL - 1.2 - 1.6 - 1.8 ns CLK to WAIT valid tKHTL - 5.5 -7 -9 ns Output HOLD from CLK tKOH 2 - 2- 2- ns CLK HIGH or LOW time tKP 3 - 3- 4- ns Output disable to DQ High-Z output tOHZ - 7 -8 -8 ns 2 Output enable to Low-Z output tOLZ 3 - 3- 3- ns 3 Setup time to active CLK edge tSP 2 - 3- 3- ns |
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