EMC326SP16AJ

2Mx16 CellularRAM

5

Preliminary

List of Tables

Table 1:

PIN Descriptions ...................................................................................................................................................... 7

Table 2:

Bus Operations ......................................................................................................................................................... 8

Table 3:

Sequence and Burst Length ..................................................................................................................................... 23

Table 4:

Drive Strength .......................................................................................................................................................... 24

Table 5:

Variable Latency Configuration Codes...................................................................................................................... 25

Table 6:

Fixed Latency Configuration Codes.......................................................................................................................... 26

Table 7:

Address Patterns for PAR(RCR[4] =1)...................................................................................................................... 28

Table 8:

Device Identification Register Mapping .................................................................................................................... 28

Table 9:

Absolute Maximum Ratings ..................................................................................................................................... 29

Table 10: Electrical Characteristics and Operating Conditions ................................................................................................. 29

Table 11:

Deep Power-Down Specifications ............................................................................................................................ 30

Table 12: Capacitance ............................................................................................................................................................. 30

Table 13: Asynchronous READ Cycle Timing Requirements ................................................................................................... 31

Table 14: Burst READ Cycle Timing Requirements ................................................................................................................. 32

Table 15: Asynchronous WRITE Cycle Timing Requirements ................................................................................................. 33

Table 16: Burst WRITE Cycle Timing Requirements ............................................................................................................... 34

Table 17: Initialization and DPD Timing Parameters ................................................................................................................ 35