H8SLASH3021 datasheet(319/712 Pages) RENESAS

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9. Programmable Timing Pattern Controller

Rev.2.00 Mar. 22, 2007 Page 295 of 684

REJ09B0352-0200

9.2.6

Next Data Register B (NDRB)

NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups

3 and 2 (pins TP

15 to TP8)*. During TPC output, when an ITU compare match event specified in

TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The address of

NDRB differs depending on whether TPC output groups 3 and 2 have the same output trigger or

different output triggers.

NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Note: Since this LSI does not have a TP

14 pin, the TP14 signal cannot be output to the outside.

Same Trigger for TPC Output Groups 3 and 2: If TPC output groups 3 and 2 are triggered by

the same compare match event, the NDRB address is H'FFA4. The upper 4 bits belong to group 3

and the lower 4 bits to group 2. Address H'FFA6 consists entirely of reserved bits that cannot be

modified and always read 1.

Address H'FFA4

Bit

Initial value

Read/Write

NDR15

R/W

NDR14

R/W

NDR13

R/W

NDR12

R/W

NDR11

R/W

NDR10

R/W

NDR9

R/W

NDR8

R/W

Next data 11 to 8

These bits store the next output

data for TPC output group 2

Next data 15 to 12

These bits store the next output

data for TPC output group 3

Address H'FFA6

Bit

Initial value

Read/Write

—

Reserved bits

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