H8SLASH3021 datasheet(323/712 Pages) RENESAS

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9. Programmable Timing Pattern Controller

Rev.2.00 Mar. 22, 2007 Page 299 of 684

REJ09B0352-0200

9.2.9

TPC Output Control Register (TPCR)

TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a

group-by-group basis.

Bit

Initial value

Read/Write

G3CMS1

R/W

G3CMS0

R/W

G2CMS1

R/W

G2CMS0

R/W

G1CMS1

R/W

G0CMS0

R/W

G1CMS0

R/W

G0CMS1

R/W

Group 3 compare

match select 1 and 0

These bits select

the compare match

event that triggers

TPC output group 3

(TP

to TP )

∗

Group 2 compare

match select 1 and 0

These bits select

the compare match

event that triggers

TPC output group 2

(TP

to TP )

Group 1 compare

match select 1 and 0

These bits select

the compare match

event that triggers

TPC output group 1

(TP to TP )

Group 0 compare

match select 1 and 0

These bits select

the compare match

event that triggers

TPC output group 0

(TP to TP )

Note: * Since this LSI does not have a TP14 pin, the TP14 signal cannot be output to the outside.

TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

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