H8SLASH3021 datasheet(320/712 Pages) RENESAS

320 / 712 page

9. Programmable Timing Pattern Controller

Rev.2.00 Mar. 22, 2007 Page 296 of 684

REJ09B0352-0200

Different Triggers for TPC Output Groups 3 and 2: If TPC output groups 3 and 2 are triggered

by different compare match events, the address of the upper 4 bits of NDRB (group 3)* is H'FFA4

and the address of the lower 4 bits (group 2) is H'FFA6. Bits 3 to 0 of address H'FFA4 and bits 7

to 4 of address H'FFA6 are reserved bits that cannot be modified and always read 1.

Note: * Since this LSI does not have a TP

14 pin, the TP14 signal cannot be output off-chip.

Address H'FFA4

Bit

Initial value

Read/Write

NDR15

R/W

NDR14

R/W

NDR13

R/W

NDR12

R/W

—

Reserved bits

Next data 15 to 12

These bits store the next output

data for TPC output group 3

Address H'FFA6

Bit

Initial value

Read/Write

—

NDR11

R/W

NDR10

R/W

NDR9

R/W

NDR8

R/W

Next data 11 to 8

These bits store the next output

data for TPC output group 2

Reserved bits

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