H8SLASH3021 datasheet(321/712 Pages) RENESAS

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9. Programmable Timing Pattern Controller

Rev.2.00 Mar. 22, 2007 Page 297 of 684

REJ09B0352-0200

9.2.7

Next Data Enable Register A (NDERA)

NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0

(TP

7 to TP0) on a bit-by-bit basis.

Bit

Initial value

Read/Write

NDER0

R/W

NDER1

R/W

NDER2

R/W

NDER3

R/W

NDER4

R/W

NDER5

R/W

NDER6

R/W

NDER7

R/W

Next data enable 7 to 0

These bits enable or disable

TPC output groups 1 and 0

If a bit is enabled for TPC output by NDERA, then when the ITU compare match event selected in

the TPC output control register (TPCR) occurs, the NDRA value is automatically transferred to

the corresponding PADR bit, updating the output value. If TPC output is disabled, the bit value is

not transferred from NDRA to PADR and the output value does not change.

NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC

output groups 1 and 0 (TP

7 to TP0) on a bit-by-bit basis.

Bits 7 to 0

NDER7 to NDER0

Description

TPC outputs TP

7 to TP0 are disabled

(NDR7 to NDR0 are not transferred to PA

7 to PA0)

(Initial value)

TPC outputs TP

7 to TP0 are enabled

(NDR7 to NDR0 are transferred to PA

7 to PA0)

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