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H8/3003 Datasheet(PDF) 333 Page - Renesas Technology Corp |
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H8/3003 Datasheet(HTML) 333 Page - Renesas Technology Corp |
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333 / 715 page  10.2.13 Timer Interrupt Enable Register (TIER) TIER is an 8-bit register. The ITU has five TIERs, one in each channel. Channel Abbreviation Function 0 TIER0 Enables or disables interrupt requests. 1 TIER1 2 TIER2 3 TIER3 4 TIER4 Each TIER is an 8-bit readable/writable register that enables and disables overflow interrupt requests and general register compare match and input capture interrupt requests. TIER is initialized to H'F8 by a reset and in standby mode. Bits 7 to 3—Reserved: Read-only bits, always read as 1. Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 2 OVIE 0 R/W 1 IMIEB 0 R/W 0 IMIEA 0 R/W Reserved bits Overflow interrupt enable Enables or disables OVF interrupts Input capture/compare match interrupt enable B Enables or disables IMFB interrupts Input capture/compare match interrupt enable A Enables or disables IMFA interrupts 315 |
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