H8SLASH3003 datasheet(67/715 Pages) RENESAS

67 / 715 page

2.8.2 Program Execution State

In this state the CPU executes program instructions in normal sequence.

2.8.3 Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU alters the normal

program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from

the exception vector table and branches to that address. In interrupt and trap exception handling

the CPU references the stack pointer (ER7) and saves the program counter and condition code

Types of Exception Handling and Their Priority: Exception handling is performed for resets,

interrupts, and trap instructions. Table 2-14 indicates the types of exception handling and their

priority. Trap instruction exceptions are accepted at all times in the program execution state.

Table 2-14 Exception Handling Types and Priority

Priority

Type of Exception Detection Timing

Start of Exception Handling

High

Reset

Synchronized with clock

Exception handling starts immediately

when

RES changes from low to high

Interrupt

End of instruction

When an interrupt is requested,

execution or end of

exception handling starts at the end of

exception handling*

the current instruction or current

exception-handling sequence

Trap instruction

When TRAPA instruction

Exception handling starts when a trap

Low

is executed

(TRAPA) instruction is executed

Note: * Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or

immediately after reset exception handling.

Figure 2-12 classifies the exception sources. For further details about exception sources, vector

numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt

Controller.

H8/3003 Datasheet(PDF) 67 Page - Renesas Technology Corp