H8SLASH3003 datasheet(16/715 Pages) RENESAS

16 / 715 page

Major Revisions and Additions in This Version

Page

Item

Description

P96

Figure 5-7

Interrupt Sequence (Mode 2,

Operation timing amended

Two-State Access, Stack in

External Memory)

P97

Table 5-5

Interrupt Response Time

Table values changed

P125

Figure 6-15

Programmable Wait Mode

Operation timing amended

P132

Figure 6-20

ASTCR Write Timing

Operation timing amended

P166

Figure 7-20

Contention between RTCNT

Operation timing amended

Write and Clear

P167

Figure 7-21

Contention between RTCNT

Operation timing amended

Write and Increment

P168

Figure 7-22

Contention between RTCOR

Address bus amended

Write and Compare Match

P175

Table 8-1

DMAC functional overview

Table contents amended

P207

Figure 8-8

Operation in Normal Mode

Signal descriptions amended

P220

Figure 8-17

Timing of DMAC Activation

Operation timing amended

by Low

DREQ Level in

Normal Mode

P270 to Table 9-16

Port B Pin Functions

Table contents amended

P272

P279

Table 9-18

Port C Pin Functions

Table contents amended

P343

Figure 10-34 Clearing Procedure for

Description added

Complementary PWM Mode

P408

Table 12-1

WDT Pin

Note deleted

P458 to Figure 13-7

Sample Flowchart for

Flowchart amended

P459

Receiving Serial Data

P480

13.5

Usage Notes

Formula amended

P506

Table 16-1

Damping Resistance Value

Values added to table

P507

Table 16-2

Crystal Resonator Parameters

Values added to table

P509

Table 16-3

Clock Timing

Table values changed

P509

Figure 16-6

External Clock Input Timing

Figure amended

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